* [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT
@ 2026-04-07 13:26 Jan Maslak
2026-04-07 13:26 ` [PATCH 2/3] lib/rendercopy: Convert rendercopy_gen9 to use genxml pack headers Jan Maslak
` (6 more replies)
0 siblings, 7 replies; 9+ messages in thread
From: Jan Maslak @ 2026-04-07 13:26 UTC (permalink / raw)
To: igt-dev; +Cc: zbigniew.kempczynski, Jan Maslak
This series brings Mesa's hardware XML command/state definitions and
gen_pack_header.py code generator into IGT, adds a new IGT-written
batch buffer decoder (gen_decode_header.py), and converts rendercopy_gen9
to use the generated pack headers.
Patch 1 imports the XML definitions and generators. gen_pack_header.py
is taken from Mesa with C90 compliance fixes and a new baseline
deduplication mechanism - when a platform's command layout matches any
older generation exactly, the item is omitted entirely.
gen_decode_header.py is a new IGT-only file that generates per-platform
decoders for instructions, structs, and registers.
Patch 2 converts rendercopy_gen9.c to use the generated pack headers,
replacing hand-written struct assignments and intel_bb_out() calls with
igt_genxml_emit and igt_genxml_pack_state.
Patch 3 adds an opt-in annotated batch dump to intel_bb_dump(): when
IGT_BB_ANNOTATE=1 is set a companion .annotated file is written alongside
the raw hex dump, decoding each command's field names and values.
Tested on LNL and DG2 (xe_render_copy render-square, render-full;
xe_intel_bb render) and TGL (gem_render_copy_redux; api_intel_bb).
Signed-off-by: Jan Maslak <jan.maslak@intel.com>
Jan Maslak (3):
lib/genxml: Import genxml definitions and generators from Mesa
lib/rendercopy: Convert rendercopy_gen9 to use genxml pack headers
lib: Add genxml annotated batch buffer decode
lib/genxml/gen110.xml | 3358 +++++++++++++++++++++++++
lib/genxml/gen120.xml | 2432 ++++++++++++++++++
lib/genxml/gen125.xml | 2628 +++++++++++++++++++
lib/genxml/gen40.xml | 1012 ++++++++
lib/genxml/gen45.xml | 507 ++++
lib/genxml/gen50.xml | 648 +++++
lib/genxml/gen60.xml | 2606 +++++++++++++++++++
lib/genxml/gen70.xml | 3067 ++++++++++++++++++++++
lib/genxml/gen75.xml | 2424 ++++++++++++++++++
lib/genxml/gen80.xml | 2993 ++++++++++++++++++++++
lib/genxml/gen90.xml | 4192 +++++++++++++++++++++++++++++++
lib/genxml/gen_decode_header.py | 487 ++++
lib/genxml/gen_pack_header.py | 799 ++++++
lib/genxml/igt_genxml.h | 112 +
lib/genxml/igt_genxml_decode.h | 60 +
lib/genxml/igt_genxml_defs.h | 335 +++
lib/genxml/intel_genxml.py | 553 ++++
lib/genxml/util.py | 39 +
lib/genxml/xe2.xml | 1969 +++++++++++++++
lib/genxml/xe3.xml | 816 ++++++
lib/genxml/xe3p.xml | 4 +
lib/intel_batchbuffer.c | 32 +-
lib/meson.build | 65 +-
lib/rendercopy_gen9.c | 1117 ++++----
24 files changed, 31687 insertions(+), 568 deletions(-)
create mode 100644 lib/genxml/gen110.xml
create mode 100644 lib/genxml/gen120.xml
create mode 100644 lib/genxml/gen125.xml
create mode 100644 lib/genxml/gen40.xml
create mode 100644 lib/genxml/gen45.xml
create mode 100644 lib/genxml/gen50.xml
create mode 100644 lib/genxml/gen60.xml
create mode 100644 lib/genxml/gen70.xml
create mode 100644 lib/genxml/gen75.xml
create mode 100644 lib/genxml/gen80.xml
create mode 100644 lib/genxml/gen90.xml
create mode 100644 lib/genxml/gen_decode_header.py
create mode 100644 lib/genxml/gen_pack_header.py
create mode 100644 lib/genxml/igt_genxml.h
create mode 100644 lib/genxml/igt_genxml_decode.h
create mode 100644 lib/genxml/igt_genxml_defs.h
create mode 100644 lib/genxml/intel_genxml.py
create mode 100644 lib/genxml/util.py
create mode 100644 lib/genxml/xe2.xml
create mode 100644 lib/genxml/xe3.xml
create mode 100644 lib/genxml/xe3p.xml
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 2/3] lib/rendercopy: Convert rendercopy_gen9 to use genxml pack headers 2026-04-07 13:26 [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT Jan Maslak @ 2026-04-07 13:26 ` Jan Maslak 2026-04-07 15:00 ` Ville Syrjälä 2026-04-07 13:26 ` [PATCH 3/3] lib: Add genxml annotated batch buffer decode Jan Maslak ` (5 subsequent siblings) 6 siblings, 1 reply; 9+ messages in thread From: Jan Maslak @ 2026-04-07 13:26 UTC (permalink / raw) To: igt-dev; +Cc: zbigniew.kempczynski, Jan Maslak Replace hand-written struct assignments and intel_bb_out() calls in rendercopy_gen9.c with igt_genxml_emit and igt_genxml_pack_state calls backed by the genxml pack headers. Command emission is now driven directly from the hardware XML definitions rather than manually maintained structs. Signed-off-by: Jan Maslak <jan.maslak@intel.com> --- lib/rendercopy_gen9.c | 1117 ++++++++++++++++++++--------------------- 1 file changed, 551 insertions(+), 566 deletions(-) diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index d44988010..eecb20a32 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -21,11 +21,17 @@ #include "intel_io.h" #include "intel_mocs.h" #include "rendercopy.h" -#include "gen9_render.h" +#include "surfaceformat.h" #include "xe2_render.h" #include "intel_reg.h" #include "igt_aux.h" #include "intel_chipset.h" +#include "genxml/igt_genxml.h" +#include "gen90_pack.h" +#include "gen110_pack.h" +#include "gen120_pack.h" +#include "gen125_pack.h" +#include "xe2_pack.h" #define VERTEX_SIZE (3*4) @@ -187,13 +193,60 @@ static uint32_t dg2_compression_format(const struct intel_buf *buf) } } -/* Mostly copy+paste from gen6, except height, width, pitch moved */ +/* + * IGT_RSS_COMMON - set RENDER_SURFACE_STATE fields shared across all gens. + * Works via C preprocessor structural typing: all gen-specific structs + * have identical field names for these members. + */ +#define IGT_RSS_COMMON(ss, buf, mocs_val, rd, wd) \ + do { \ + ss.SurfaceType = GFX9_SURFTYPE_2D; \ + ss.SurfaceFormat = gen4_surface_format((buf)->bpp, \ + (buf)->depth); \ + ss.SurfaceVerticalAlignment = GFX9_VALIGN_4; \ + ss.MOCS = (mocs_val); \ + ss.Width = intel_buf_width(buf) - 1; \ + ss.Height = intel_buf_height(buf) - 1; \ + ss.SurfacePitch = (buf)->surface[0].stride - 1; \ + ss.ShaderChannelSelectRed = (int)GFX9_SCS_RED; \ + ss.ShaderChannelSelectGreen = (int)GFX9_SCS_GREEN; \ + ss.ShaderChannelSelectBlue = (int)GFX9_SCS_BLUE; \ + ss.ShaderChannelSelectAlpha = (int)GFX9_SCS_ALPHA; \ + ss.SurfaceBaseAddress = \ + igt_address_of((buf), (buf)->surface[0].offset, \ + (rd), (wd)); \ + } while (0) + +/* + * IGT_RSS_TILING - set TileMode from buf->tiling. The numeric encoding is + * identical across gen9/gen12/gen12.5/xe2, but the enum names differ per gen. + * We use xe2 (GFX20) names as they best reflect the modern tile semantics; + * (int) casts suppress -Wenum-conversion when used with older-gen structs. + */ +#define IGT_RSS_TILING(ss, buf) \ + do { \ + switch ((buf)->tiling) { \ + case I915_TILING_NONE: \ + ss.TileMode = (int)GFX20_LINEAR; \ + break; \ + case I915_TILING_X: \ + ss.TileMode = (int)GFX20_XMAJOR; \ + break; \ + case I915_TILING_64: \ + ss.TileMode = (int)GFX20_TILE64; \ + ss.MipTailStartLOD = 0xf; \ + break; \ + default: \ + ss.TileMode = (int)GFX20_TILE4; \ + } \ + } while (0) + static uint32_t -gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst, - bool fast_clear) { - struct gen9_surface_state *ss; +gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) { uint32_t write_domain, read_domain; - uint64_t address; + unsigned int gen = intel_gen(ibb->devid); + uint32_t mocs; + void *ss_ptr; igt_assert_lte(buf->surface[0].stride, 256*1024); igt_assert_lte(intel_buf_width(buf), 16384); @@ -206,120 +259,106 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst, read_domain = I915_GEM_DOMAIN_SAMPLER; } - ss = intel_bb_ptr_align(ibb, 64); - - ss->ss0.surface_type = SURFACE_2D; - ss->ss0.surface_format = gen4_surface_format(buf->bpp, buf->depth); - ss->ss0.vertical_alignment = 1; /* align 4 */ - ss->ss0.horizontal_alignment = 1; /* align 4 or HALIGN_32 on display ver >= 13*/ + /* MOCS encoding: genxml has a single 7-bit MOCS field (bits 30:24). + * The old struct had mocs_index:6 at bits 30:25 and pxp:1 at bit 24. + * Reproduce the same bit layout. */ + mocs = (buf->mocs_index << 1) | (intel_buf_pxp(buf) ? 1 : 0); - ss->ss1.mocs_index = buf->mocs_index; + ss_ptr = intel_bb_ptr_align(ibb, 64); - if (HAS_4TILE(ibb->devid)) { - ss->ss5.mip_tail_start_lod = 0; - } else { - ss->ss0.render_cache_read_write = 1; - ss->ss5.mip_tail_start_lod = 1; /* needed with trmode */ - } - - switch (buf->tiling) { - case I915_TILING_NONE: - ss->ss0.tiled_mode = 0; - break; - case I915_TILING_X: - ss->ss0.tiled_mode = 2; - break; - case I915_TILING_64: - ss->ss0.tiled_mode = 1; - ss->ss5.mip_tail_start_lod = 0xf; - break; - default: - ss->ss0.tiled_mode = 3; - if (buf->tiling == I915_TILING_Yf) - ss->ss5.trmode = 1; - else if (buf->tiling == I915_TILING_Ys) - ss->ss5.trmode = 2; - break; - } + if (gen >= 20) { + /* ── Xe2 (LNL+) ── */ + igt_genxml_pack_state(ibb, GFX20_RENDER_SURFACE_STATE, ss_ptr, ss) { + IGT_RSS_COMMON(ss, buf, mocs, read_domain, write_domain); + IGT_RSS_TILING(ss, buf); + ss.SurfaceHorizontalAlignment = GFX20_HALIGN_32; - if (intel_buf_pxp(buf)) - ss->ss1.pxp = 1; - - address = intel_bb_offset_reloc_with_delta(ibb, buf->handle, - read_domain, write_domain, - buf->surface[0].offset, - intel_bb_offset(ibb) + 4 * 8, - buf->addr.offset); - ss->ss8.base_addr = (address + buf->surface[0].offset); - ss->ss9.base_addr_hi = (address + buf->surface[0].offset) >> 32; - - ss->ss2.height = intel_buf_height(buf) - 1; - ss->ss2.width = intel_buf_width(buf) - 1; - ss->ss3.pitch = buf->surface[0].stride - 1; - - ss->ss7.skl.shader_chanel_select_r = 4; - ss->ss7.skl.shader_chanel_select_g = 5; - ss->ss7.skl.shader_chanel_select_b = 6; - ss->ss7.skl.shader_chanel_select_a = 7; - - if (buf->compression == I915_COMPRESSION_MEDIA) - ss->ss7.tgl.media_compression = 1; - else if (buf->compression == I915_COMPRESSION_RENDER) { - if (intel_gen(ibb->devid) >= 20) - ss->ss6.aux_mode = 0x0; /* AUX_NONE, unified compression */ - else - ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */ - - if (intel_gen(ibb->devid) < 12 && buf->ccs[0].stride) { - ss->ss6.aux_pitch = (buf->ccs[0].stride / 128) - 1; - - address = intel_bb_offset_reloc_with_delta(ibb, buf->handle, - read_domain, write_domain, - (buf->cc.offset ? (1 << 10) : 0) - | buf->ccs[0].offset, - intel_bb_offset(ibb) + 4 * 10, - buf->addr.offset); - ss->ss10.aux_base_addr = (address + buf->ccs[0].offset) >> 12; - ss->ss11.aux_base_addr_hi = (address + buf->ccs[0].offset) >> 32; + if (buf->compression == I915_COMPRESSION_RENDER) { + ss.AuxiliarySurfaceMode = GFX20_AUX_NONE; + ss.CompressionFormat = lnl_compression_format(buf); + } } - if (buf->cc.offset) { - igt_assert(buf->compression == I915_COMPRESSION_RENDER); - - ss->ss10.clearvalue_addr_enable = 1; - - address = intel_bb_offset_reloc_with_delta(ibb, buf->handle, - read_domain, write_domain, - buf->cc.offset, - intel_bb_offset(ibb) + 4 * 12, - buf->addr.offset); - - /* - * If this assert doesn't hold below clear address will be - * written wrong. - */ - - igt_assert(__builtin_ctzl(address + buf->cc.offset) >= 6 && - (__builtin_clzl(address + buf->cc.offset) >= 16)); - - ss->ss12.dg2.clear_address = (address + buf->cc.offset) >> 6; - ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32; + } else if (HAS_4TILE(ibb->devid)) { + /* ── Gen12.5 / DG2 ── */ + igt_genxml_pack_state(ibb, GFX125_RENDER_SURFACE_STATE, ss_ptr, ss) { + IGT_RSS_COMMON(ss, buf, mocs, read_domain, write_domain); + IGT_RSS_TILING(ss, buf); + ss.SurfaceHorizontalAlignment = GFX125_HALIGN_32; + + if (buf->compression == I915_COMPRESSION_MEDIA) { + ss.MemoryCompressionEnable = true; + ss.MemoryCompressionMode = GFX125_MEDIACOMPRESSION; + } else if (buf->compression == I915_COMPRESSION_RENDER) { + ss.AuxiliarySurfaceMode = GFX125_AUX_CCS_E; + ss.CompressionFormat = dg2_compression_format(buf); + + if (buf->cc.offset) { + ss.ClearValueAddressEnable = true; + ss.ClearValueAddress = + igt_address_of(buf, buf->cc.offset, + read_domain, write_domain); + } + } } - if (HAS_4TILE(ibb->devid)) { - ss->ss7.dg2.memory_compression_type = 0; - ss->ss7.dg2.memory_compression_enable = 0; - ss->ss7.dg2.disable_support_for_multi_gpu_partial_writes = 1; - ss->ss7.dg2.disable_support_for_multi_gpu_atomics = 1; + } else if (gen >= 12) { + /* ── Gen12 / TGL ── */ + igt_genxml_pack_state(ibb, GFX12_RENDER_SURFACE_STATE, ss_ptr, ss) { + IGT_RSS_COMMON(ss, buf, mocs, read_domain, write_domain); + IGT_RSS_TILING(ss, buf); + ss.SurfaceHorizontalAlignment = GFX12_HALIGN_4; + ss.RenderCacheReadWriteMode = GFX12_READWRITECACHE; + ss.MipTailStartLOD = 1; + + if (buf->compression == I915_COMPRESSION_MEDIA) { + ss.MemoryCompressionEnable = true; + ss.MemoryCompressionMode = GFX12_HORIZONTAL; + } else if (buf->compression == I915_COMPRESSION_RENDER) { + ss.AuxiliarySurfaceMode = GFX12_AUX_CCS_E; + + if (buf->cc.offset) { + ss.ClearValueAddressEnable = true; + ss.ClearValueAddress = + igt_address_of(buf, buf->cc.offset, + read_domain, write_domain); + } + } + } - if (intel_gen(ibb->devid) >= 20) - ss->ss12.lnl.compression_format = lnl_compression_format(buf); - else - ss->ss12.dg2.compression_format = dg2_compression_format(buf); + } else { + /* ── Gen9 / Gen11 ── */ + igt_genxml_pack_state(ibb, GFX9_RENDER_SURFACE_STATE, ss_ptr, ss) { + IGT_RSS_COMMON(ss, buf, mocs, read_domain, write_domain); + IGT_RSS_TILING(ss, buf); + ss.SurfaceHorizontalAlignment = GFX9_HALIGN_4; + ss.RenderCacheReadWriteMode = GFX9_READWRITECACHE; + ss.MipTailStartLOD = 1; + + if (buf->tiling == I915_TILING_Yf) + ss.TiledResourceMode = GFX9_TILEYF; + else if (buf->tiling == I915_TILING_Ys) + ss.TiledResourceMode = GFX9_TILEYS; + + if (buf->compression == I915_COMPRESSION_MEDIA) { + ss.MemoryCompressionEnable = true; + ss.MemoryCompressionMode = GFX9_HORIZONTAL; + } else if (buf->compression == I915_COMPRESSION_RENDER) { + ss.AuxiliarySurfaceMode = GFX9_AUX_CCS_E; + + if (buf->ccs[0].stride) { + ss.AuxiliarySurfacePitch = + (buf->ccs[0].stride / 128) - 1; + ss.AuxiliarySurfaceBaseAddress = + igt_address_of(buf, buf->ccs[0].offset, + read_domain, write_domain); + } + } } } - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*ss)); + return intel_bb_ptr_add_return_prev_offset(ibb, + GFX9_RENDER_SURFACE_STATE_length * 4); } static uint32_t @@ -328,15 +367,14 @@ gen8_bind_surfaces(struct intel_bb *ibb, const struct intel_buf *dst) { uint32_t *binding_table, binding_table_offset; - bool fast_clear = !src; binding_table = intel_bb_ptr_align(ibb, 32); binding_table_offset = intel_bb_ptr_add_return_prev_offset(ibb, 32); - binding_table[0] = gen9_bind_buf(ibb, dst, 1, fast_clear); + binding_table[0] = gen9_bind_buf(ibb, dst, 1); if (src != NULL) - binding_table[1] = gen9_bind_buf(ibb, src, 0, false); + binding_table[1] = gen9_bind_buf(ibb, src, 0); return binding_table_offset; } @@ -344,21 +382,18 @@ gen8_bind_surfaces(struct intel_bb *ibb, /* Mostly copy+paste from gen6, except wrap modes moved */ static uint32_t gen8_create_sampler(struct intel_bb *ibb) { - struct gen8_sampler_state *ss; - - ss = intel_bb_ptr_align(ibb, 64); - - ss->ss0.min_filter = GEN4_MAPFILTER_NEAREST; - ss->ss0.mag_filter = GEN4_MAPFILTER_NEAREST; - ss->ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; - ss->ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; - ss->ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; - - /* I've experimented with non-normalized coordinates and using the LD - * sampler fetch, but couldn't make it work. */ - ss->ss3.non_normalized_coord = 0; + void *ptr = intel_bb_ptr_align(ibb, 64); + + igt_genxml_pack_state(ibb, GFX9_SAMPLER_STATE, ptr, ss) { + ss.MinModeFilter = GFX9_MAPFILTER_NEAREST; + ss.MagModeFilter = GFX9_MAPFILTER_NEAREST; + ss.TCZAddressControlMode = GFX9_TCM_CLAMP; + ss.TCYAddressControlMode = GFX9_TCM_CLAMP; + ss.TCXAddressControlMode = GFX9_TCM_CLAMP; + } - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*ss)); + return intel_bb_ptr_add_return_prev_offset(ibb, + GFX9_SAMPLER_STATE_length * 4); } static uint32_t @@ -531,50 +566,62 @@ gen7_fill_vertex_buffer_data(struct intel_bb *ibb, */ static void gen6_emit_vertex_elements(struct intel_bb *ibb) { + void *ve_ptr; + /* * The VUE layout * dword 0-3: pad (0, 0, 0. 0) * dword 4-7: position (x, y, 0, 1.0), * dword 8-11: texture coordinate 0 (u0, v0, 0, 1.0) */ - intel_bb_out(ibb, GEN4_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2)); + { + struct GFX9_3DSTATE_VERTEX_ELEMENTS ves = { GFX9_3DSTATE_VERTEX_ELEMENTS_header }; + ves.DWordLength = 3 * GFX9_VERTEX_ELEMENT_STATE_length - 1; + GFX9_3DSTATE_VERTEX_ELEMENTS_pack(ibb, intel_bb_ptr(ibb), &ves); + intel_bb_ptr_add(ibb, 4); + } - /* Element state 0. These are 4 dwords of 0 required for the VUE format. - * We don't really know or care what they do. - */ - intel_bb_out(ibb, 0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | - SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | - 0 << VE0_OFFSET_SHIFT); /* we specify 0, but it's really does not exist */ - intel_bb_out(ibb, GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); - - /* Element state 1 - Our "destination" vertices. These are passed down - * through the pipeline, and eventually make it to the pixel shader as - * the offsets in the destination surface. It's packed as the 16 - * signed/scaled because of gen6 rendercopy. I see no particular reason - * for doing this though. - */ - intel_bb_out(ibb, 0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | - SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | - 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */ - intel_bb_out(ibb, GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); - - /* Element state 2. Last but not least we store the U,V components as - * normalized floats. These will be used in the pixel shader to sample - * from the source buffer. - */ - intel_bb_out(ibb, 0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | - SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT | - 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */ - intel_bb_out(ibb, GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + /* Element state 0. These are 4 dwords of 0 required for the VUE format. */ + ve_ptr = intel_bb_ptr(ibb); + igt_genxml_pack_state(ibb, GFX9_VERTEX_ELEMENT_STATE, ve_ptr, ve0) { + ve0.VertexBufferIndex = 0; + ve0.Valid = true; + ve0.SourceElementFormat = SURFACEFORMAT_R32G32B32A32_FLOAT; + ve0.SourceElementOffset = 0; + ve0.Component0Control = GFX9_VFCOMP_STORE_0; + ve0.Component1Control = GFX9_VFCOMP_STORE_0; + ve0.Component2Control = GFX9_VFCOMP_STORE_0; + ve0.Component3Control = GFX9_VFCOMP_STORE_0; + } + intel_bb_ptr_add(ibb, GFX9_VERTEX_ELEMENT_STATE_length * 4); + + /* Element state 1 - destination vertices (16-bit signed/scaled). */ + ve_ptr = intel_bb_ptr(ibb); + igt_genxml_pack_state(ibb, GFX9_VERTEX_ELEMENT_STATE, ve_ptr, ve1) { + ve1.VertexBufferIndex = 0; + ve1.Valid = true; + ve1.SourceElementFormat = SURFACEFORMAT_R16G16_SSCALED; + ve1.SourceElementOffset = 0; + ve1.Component0Control = GFX9_VFCOMP_STORE_SRC; + ve1.Component1Control = GFX9_VFCOMP_STORE_SRC; + ve1.Component2Control = GFX9_VFCOMP_STORE_0; + ve1.Component3Control = GFX9_VFCOMP_STORE_1_FP; + } + intel_bb_ptr_add(ibb, GFX9_VERTEX_ELEMENT_STATE_length * 4); + + /* Element state 2 - texture coordinates (normalized floats). */ + ve_ptr = intel_bb_ptr(ibb); + igt_genxml_pack_state(ibb, GFX9_VERTEX_ELEMENT_STATE, ve_ptr, ve2) { + ve2.VertexBufferIndex = 0; + ve2.Valid = true; + ve2.SourceElementFormat = SURFACEFORMAT_R32G32_FLOAT; + ve2.SourceElementOffset = 4; + ve2.Component0Control = GFX9_VFCOMP_STORE_SRC; + ve2.Component1Control = GFX9_VFCOMP_STORE_SRC; + ve2.Component2Control = GFX9_VFCOMP_STORE_0; + ve2.Component3Control = GFX9_VFCOMP_STORE_1_FP; + } + intel_bb_ptr_add(ibb, GFX9_VERTEX_ELEMENT_STATE_length * 4); } /* @@ -585,161 +632,185 @@ gen6_emit_vertex_elements(struct intel_bb *ibb) { */ static void gen7_emit_vertex_buffer(struct intel_bb *ibb, uint32_t offset) { - intel_bb_out(ibb, GEN4_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2)); - intel_bb_out(ibb, 0 << GEN6_VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */ - GEN8_VB0_BUFFER_ADDR_MOD_EN | /* Address Modify Enable */ - VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT); - intel_bb_emit_reloc(ibb, ibb->handle, - I915_GEM_DOMAIN_VERTEX, 0, - offset, ibb->batch_offset); - intel_bb_out(ibb, 3 * VERTEX_SIZE); + void *vb_ptr; + + /* Variable-length: 1 header dword + VERTEX_BUFFER_STATE element */ + { + struct GFX9_3DSTATE_VERTEX_BUFFERS vbs = { GFX9_3DSTATE_VERTEX_BUFFERS_header }; + /* Default DWordLength=3 is correct for 1 element (1 + 4 - 2 = 3) */ + GFX9_3DSTATE_VERTEX_BUFFERS_pack(ibb, intel_bb_ptr(ibb), &vbs); + intel_bb_ptr_add(ibb, 4); + } + + vb_ptr = intel_bb_ptr(ibb); + igt_genxml_pack_state(ibb, GFX9_VERTEX_BUFFER_STATE, vb_ptr, vb) { + vb.VertexBufferIndex = 0; + vb.AddressModifyEnable = true; + vb.MOCS = intel_get_wb_mocs_index(ibb->fd); + vb.BufferPitch = VERTEX_SIZE; + vb.BufferStartingAddress = (struct igt_address){ + .offset = ibb->batch_offset + offset, + .handle = ibb->handle, + .read_domains = I915_GEM_DOMAIN_VERTEX, + .write_domain = 0, + .presumed_offset = ibb->batch_offset, + }; + vb.BufferSize = 3 * VERTEX_SIZE; + } + intel_bb_ptr_add(ibb, GFX9_VERTEX_BUFFER_STATE_length * 4); } static uint32_t gen6_create_cc_state(struct intel_bb *ibb) { - struct gen6_color_calc_state *cc_state; + void *ptr = intel_bb_ptr_align(ibb, 64); - cc_state = intel_bb_ptr_align(ibb, 64); + igt_genxml_pack_state(ibb, GFX9_COLOR_CALC_STATE, ptr, cc_state) { } - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*cc_state)); + return intel_bb_ptr_add_return_prev_offset(ibb, + GFX9_COLOR_CALC_STATE_length * 4); } static uint32_t gen8_create_blend_state(struct intel_bb *ibb) { - struct gen8_blend_state *blend; - int i; - - blend = intel_bb_ptr_align(ibb, 64); - - for (i = 0; i < 16; i++) { - blend->bs[i].dest_blend_factor = GEN6_BLENDFACTOR_ZERO; - blend->bs[i].source_blend_factor = GEN6_BLENDFACTOR_ONE; - blend->bs[i].color_blend_func = GEN6_BLENDFUNCTION_ADD; - blend->bs[i].pre_blend_color_clamp = 1; - blend->bs[i].color_buffer_blend = 0; + void *ptr = intel_bb_ptr_align(ibb, 64); + + /* Blend state header (1 dword) - all defaults (zeros) */ + igt_genxml_pack_state(ibb, GFX9_BLEND_STATE, ptr, bs) { } + ptr += GFX9_BLEND_STATE_length * 4; + + /* 16 per-RT blend state entries */ + for (int i = 0; i < 16; i++) { + igt_genxml_pack_state(ibb, GFX9_BLEND_STATE_ENTRY, ptr, entry) { + entry.DestinationBlendFactor = GFX9_BLENDFACTOR_ZERO; + entry.SourceBlendFactor = GFX9_BLENDFACTOR_ONE; + entry.ColorBlendFunction = GFX9_BLENDFUNCTION_ADD; + entry.PreBlendColorClampEnable = true; + } + ptr += GFX9_BLEND_STATE_ENTRY_length * 4; } - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*blend)); + return intel_bb_ptr_add_return_prev_offset(ibb, + (GFX9_BLEND_STATE_length + 16 * GFX9_BLEND_STATE_ENTRY_length) * 4); } static uint32_t gen6_create_cc_viewport(struct intel_bb *ibb) { - struct gen4_cc_viewport *vp; - - vp = intel_bb_ptr_align(ibb, 32); + void *ptr = intel_bb_ptr_align(ibb, 32); - /* XXX I don't understand this */ - vp->min_depth = -1.e35; - vp->max_depth = 1.e35; + igt_genxml_pack_state(ibb, GFX9_CC_VIEWPORT, ptr, vp) { + vp.MinimumDepth = -1.e35; + vp.MaximumDepth = 1.e35; + } - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*vp)); + return intel_bb_ptr_add_return_prev_offset(ibb, + GFX9_CC_VIEWPORT_length * 4); } static uint32_t gen7_create_sf_clip_viewport(struct intel_bb *ibb) { - /* XXX these are likely not needed */ - struct gen7_sf_clip_viewport *scv_state; - - scv_state = intel_bb_ptr_align(ibb, 64); + void *ptr = intel_bb_ptr_align(ibb, 64); - scv_state->guardband.xmin = 0; - scv_state->guardband.xmax = 1.0f; - scv_state->guardband.ymin = 0; - scv_state->guardband.ymax = 1.0f; + igt_genxml_pack_state(ibb, GFX9_SF_CLIP_VIEWPORT, ptr, scv) { + scv.XMinClipGuardband = 0; + scv.XMaxClipGuardband = 1.0f; + scv.YMinClipGuardband = 0; + scv.YMaxClipGuardband = 1.0f; + } - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*scv_state)); + return intel_bb_ptr_add_return_prev_offset(ibb, + GFX9_SF_CLIP_VIEWPORT_length * 4); } static uint32_t gen6_create_scissor_rect(struct intel_bb *ibb) { - struct gen6_scissor_rect *scissor; + void *ptr = intel_bb_ptr_align(ibb, 64); - scissor = intel_bb_ptr_align(ibb, 64); + igt_genxml_pack_state(ibb, GFX9_SCISSOR_RECT, ptr, sr) { } - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*scissor)); + return intel_bb_ptr_add_return_prev_offset(ibb, + GFX9_SCISSOR_RECT_length * 4); } static void gen8_emit_sip(struct intel_bb *ibb) { - intel_bb_out(ibb, GEN4_STATE_SIP | (3 - 2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_STATE_SIP, sip) { + /* SystemInstructionPointer left as zero */ + } } static void gen7_emit_push_constants(struct intel_bb *ibb) { - intel_bb_out(ibb, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS, vs) { } + igt_genxml_emit(ibb, GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS, hs) { } + igt_genxml_emit(ibb, GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS, ds) { } + igt_genxml_emit(ibb, GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS, gs) { } + igt_genxml_emit(ibb, GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS, ps) { } } +/* + * IGT_SBA_COMMON - shared STATE_BASE_ADDRESS fields across gen9/gen11/gen125. + * All three variants have identical field names for the fields we set. + */ +#define IGT_SBA_COMMON(sba, mocs_val, surf, dyn, inst) \ + do { \ + sba.GeneralStateBaseAddressModifyEnable = true; \ + sba.GeneralStateMOCS = (mocs_val); \ + sba.StatelessDataPortAccessMOCS = (mocs_val); \ + sba.SurfaceStateBaseAddressModifyEnable = true; \ + sba.SurfaceStateMOCS = (mocs_val); \ + sba.SurfaceStateBaseAddress = (surf); \ + sba.DynamicStateBaseAddressModifyEnable = true; \ + sba.DynamicStateMOCS = (mocs_val); \ + sba.DynamicStateBaseAddress = (dyn); \ + sba.IndirectObjectMOCS = (mocs_val); \ + sba.InstructionBaseAddressModifyEnable = true; \ + sba.InstructionMOCS = (mocs_val); \ + sba.InstructionBaseAddress = (inst); \ + sba.GeneralStateBufferSizeModifyEnable = true; \ + sba.GeneralStateBufferSize = 0xfffff; \ + sba.DynamicStateBufferSizeModifyEnable = true; \ + sba.DynamicStateBufferSize = 1; \ + sba.IndirectObjectBufferSizeModifyEnable = true; \ + sba.IndirectObjectBufferSize = 0xfffff; \ + sba.InstructionBuffersizeModifyEnable = true; \ + sba.InstructionBufferSize = 1; \ + sba.BindlessSurfaceStateMOCS = (mocs_val); \ + } while (0) + static void gen9_emit_state_base_address(struct intel_bb *ibb) { + uint8_t mocs = intel_get_wb_mocs_index(ibb->fd); - /* WaBindlessSurfaceStateModifyEnable:skl,bxt */ - /* The length has to be one less if we dont modify - bindless state */ - if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) - intel_bb_out(ibb, GEN4_STATE_BASE_ADDRESS | 20); - else - intel_bb_out(ibb, GEN4_STATE_BASE_ADDRESS | (19 - 1 - 2)); - - /* general */ - intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); - intel_bb_out(ibb, 0); - - /* stateless data port */ - intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); - - /* surface */ - intel_bb_emit_reloc(ibb, ibb->handle, - I915_GEM_DOMAIN_SAMPLER, 0, - BASE_ADDRESS_MODIFY, ibb->batch_offset); - - /* dynamic */ - intel_bb_emit_reloc(ibb, ibb->handle, - I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, - BASE_ADDRESS_MODIFY, ibb->batch_offset); - - /* indirect */ - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - /* instruction */ - intel_bb_emit_reloc(ibb, ibb->handle, - I915_GEM_DOMAIN_INSTRUCTION, 0, - BASE_ADDRESS_MODIFY, ibb->batch_offset); - - /* general state buffer size */ - intel_bb_out(ibb, 0xfffff000 | 1); - /* dynamic state buffer size */ - intel_bb_out(ibb, 1 << 12 | 1); - /* indirect object buffer size */ - intel_bb_out(ibb, 0xfffff000 | 1); - /* intruction buffer size */ - intel_bb_out(ibb, 1 << 12 | 1); - - /* Bindless surface state base address */ - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); + struct igt_address surf_base = + igt_address_of_batch(ibb, I915_GEM_DOMAIN_SAMPLER, 0); + struct igt_address dyn_base = + igt_address_of_batch(ibb, + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0); + struct igt_address inst_base = + igt_address_of_batch(ibb, I915_GEM_DOMAIN_INSTRUCTION, 0); - if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) { - /* Bindless sampler */ - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); + if (HAS_4TILE(ibb->devid) || intel_gen(ibb->devid) > 12) { + igt_genxml_emit(ibb, GFX125_STATE_BASE_ADDRESS, sba) { + IGT_SBA_COMMON(sba, mocs, surf_base, dyn_base, inst_base); + /* WBP (0) and UC (1) are marked dont_use in the XML for this field. */ + sba.L1CacheControl = GFX125_L1CC_WB; + sba.BindlessSamplerStateBaseAddressModifyEnable = true; + sba.BindlessSamplerStateMOCS = mocs; + } + } else if (intel_gen(ibb->devid) >= 11) { + igt_genxml_emit(ibb, GFX11_STATE_BASE_ADDRESS, sba) { + IGT_SBA_COMMON(sba, mocs, surf_base, dyn_base, inst_base); + sba.BindlessSamplerStateBaseAddressModifyEnable = true; + sba.BindlessSamplerStateMOCS = mocs; + } + } else { + igt_genxml_emit(ibb, GFX9_STATE_BASE_ADDRESS, sba) { + IGT_SBA_COMMON(sba, mocs, surf_base, dyn_base, inst_base); + } } } @@ -750,184 +821,119 @@ gen7_emit_urb(struct intel_bb *ibb) { const int vs_size = 2; const int vs_start = 4; - intel_bb_out(ibb, GEN7_3DSTATE_URB_VS); - intel_bb_out(ibb, vs_entries | ((vs_size - 1) << 16) | (vs_start << 25)); - intel_bb_out(ibb, GEN7_3DSTATE_URB_GS); - intel_bb_out(ibb, vs_start << 25); - intel_bb_out(ibb, GEN7_3DSTATE_URB_HS); - intel_bb_out(ibb, vs_start << 25); - intel_bb_out(ibb, GEN7_3DSTATE_URB_DS); - intel_bb_out(ibb, vs_start << 25); + igt_genxml_emit(ibb, GFX9_3DSTATE_URB_VS, urb) { + urb.VSNumberofURBEntries = vs_entries; + urb.VSURBEntryAllocationSize = vs_size - 1; + urb.VSURBStartingAddress = vs_start; + } + igt_genxml_emit(ibb, GFX9_3DSTATE_URB_GS, urb) { + urb.GSURBStartingAddress = vs_start; + } + igt_genxml_emit(ibb, GFX9_3DSTATE_URB_HS, urb) { + urb.HSURBStartingAddress = vs_start; + } + igt_genxml_emit(ibb, GFX9_3DSTATE_URB_DS, urb) { + urb.DSURBStartingAddress = vs_start; + } } static void gen8_emit_cc(struct intel_bb *ibb) { - intel_bb_out(ibb, GEN7_3DSTATE_BLEND_STATE_POINTERS); - intel_bb_out(ibb, cc.blend_state | 1); + igt_genxml_emit(ibb, GFX9_3DSTATE_BLEND_STATE_POINTERS, bsp) { + bsp.BlendStatePointer = cc.blend_state; + bsp.BlendStatePointerValid = true; + } - intel_bb_out(ibb, GEN6_3DSTATE_CC_STATE_POINTERS); - intel_bb_out(ibb, cc.cc_state | 1); + igt_genxml_emit(ibb, GFX9_3DSTATE_CC_STATE_POINTERS, ccp) { + ccp.ColorCalcStatePointer = cc.cc_state; + ccp.ColorCalcStatePointerValid = true; + } } static void gen8_emit_multisample(struct intel_bb *ibb) { - intel_bb_out(ibb, GEN8_3DSTATE_MULTISAMPLE | 0); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_3DSTATE_MULTISAMPLE, ms) { } - intel_bb_out(ibb, GEN6_3DSTATE_SAMPLE_MASK); - intel_bb_out(ibb, 1); + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLE_MASK, sm) { + sm.SampleMask = 1; + } } static void gen8_emit_vs(struct intel_bb *ibb) { - intel_bb_out(ibb, GEN6_3DSTATE_CONSTANT_VS | (11-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN6_3DSTATE_VS | (9-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_3DSTATE_CONSTANT_VS, cvs) { + cvs.MOCS = intel_get_wb_mocs_index(ibb->fd); + } + + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS, bt) { } + + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS, sp) { } + + igt_genxml_emit(ibb, GFX9_3DSTATE_VS, vs) { } } static void gen8_emit_hs(struct intel_bb *ibb) { - intel_bb_out(ibb, GEN7_3DSTATE_CONSTANT_HS | (11-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN7_3DSTATE_HS | (9-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_3DSTATE_CONSTANT_HS, chs) { + chs.MOCS = intel_get_wb_mocs_index(ibb->fd); + } + + if (intel_gen(ibb->devid) >= 20) + igt_genxml_emit(ibb, GFX20_3DSTATE_HS, hs) { } + else + igt_genxml_emit(ibb, GFX9_3DSTATE_HS, hs) { } + + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS, bt) { } + + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS, sp) { } } static void gen8_emit_gs(struct intel_bb *ibb) { - intel_bb_out(ibb, GEN6_3DSTATE_CONSTANT_GS | (11-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN6_3DSTATE_GS | (10-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_3DSTATE_CONSTANT_GS, cgs) { + cgs.MOCS = intel_get_wb_mocs_index(ibb->fd); + } + + igt_genxml_emit(ibb, GFX9_3DSTATE_GS, gs) { } + + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS, bt) { } + + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS, sp) { } } static void gen9_emit_ds(struct intel_bb *ibb) { - intel_bb_out(ibb, GEN7_3DSTATE_CONSTANT_DS | (11-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN7_3DSTATE_DS | (11-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_3DSTATE_CONSTANT_DS, cds) { + cds.MOCS = intel_get_wb_mocs_index(ibb->fd); + } + + igt_genxml_emit(ibb, GFX9_3DSTATE_DS, ds) { } + + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS, bt) { } + + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS, sp) { } } static void gen8_emit_wm_hz_op(struct intel_bb *ibb) { if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) { - intel_bb_out(ibb, GEN8_3DSTATE_WM_HZ_OP | (6-2)); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX20_3DSTATE_WM_HZ_OP, hz) { } } else { - intel_bb_out(ibb, GEN8_3DSTATE_WM_HZ_OP | (5-2)); + igt_genxml_emit(ibb, GFX9_3DSTATE_WM_HZ_OP, hz) { } } - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); } static void gen8_emit_null_state(struct intel_bb *ibb) { gen8_emit_wm_hz_op(ibb); gen8_emit_hs(ibb); - intel_bb_out(ibb, GEN7_3DSTATE_TE | (4-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); + + if (intel_gen(ibb->devid) >= 12) + igt_genxml_emit(ibb, GFX12_3DSTATE_TE, te) { } + else + igt_genxml_emit(ibb, GFX9_3DSTATE_TE, te) { } + gen8_emit_gs(ibb); gen9_emit_ds(ibb); gen8_emit_vs(ibb); @@ -935,137 +941,109 @@ gen8_emit_null_state(struct intel_bb *ibb) { static void gen7_emit_clip(struct intel_bb *ibb) { - intel_bb_out(ibb, GEN6_3DSTATE_CLIP | (4 - 2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); /* pass-through */ - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_3DSTATE_CLIP, clip) { + /* All fields zero = pass-through */ + } } static void gen8_emit_sf(struct intel_bb *ibb) { - int i; - - intel_bb_out(ibb, GEN7_3DSTATE_SBE | (6 - 2)); - intel_bb_out(ibb, 1 << GEN7_SBE_NUM_OUTPUTS_SHIFT | - GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH | - GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET | - 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT | - 1 << GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, GEN9_SBE_ACTIVE_COMPONENT_XYZW << 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN8_3DSTATE_SBE_SWIZ | (11 - 2)); - for (i = 0; i < 8; i++) - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN8_3DSTATE_RASTER | (5 - 2)); - intel_bb_out(ibb, GEN8_RASTER_FRONT_WINDING_CCW | GEN8_RASTER_CULL_NONE); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN6_3DSTATE_SF | (4 - 2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_3DSTATE_SBE, sbe) { + sbe.NumberofSFOutputAttributes = 1; + sbe.ForceVertexURBEntryReadLength = true; + sbe.ForceVertexURBEntryReadOffset = true; + sbe.VertexURBEntryReadLength = 1; + sbe.VertexURBEntryReadOffset = 1; + sbe.AttributeActiveComponentFormat[0] = GFX9_ACTIVE_COMPONENT_XYZW; + } + + igt_genxml_emit(ibb, GFX9_3DSTATE_SBE_SWIZ, swiz) { } + + igt_genxml_emit(ibb, GFX9_3DSTATE_RASTER, raster) { + raster.FrontWinding = 1; /* CCW */ + raster.CullMode = GFX9_CULLMODE_NONE; + } + + igt_genxml_emit(ibb, GFX9_3DSTATE_SF, sf) { } } static void gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel, bool fast_clear) { const int max_threads = 63; - intel_bb_out(ibb, GEN6_3DSTATE_WM | (2 - 2)); - intel_bb_out(ibb, /* XXX: I don't understand the BARYCENTRIC stuff, but it - * appears we need it to put our setup data in the place we - * expect (g6, see below) */ - GEN8_3DSTATE_PS_PERSPECTIVE_PIXEL_BARYCENTRIC); - - intel_bb_out(ibb, GEN6_3DSTATE_CONSTANT_PS | (11-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN7_3DSTATE_PS | (12-2)); - if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) - intel_bb_out(ibb, kernel | 1); - else - intel_bb_out(ibb, kernel); - intel_bb_out(ibb, 0); /* kernel hi */ + igt_genxml_emit(ibb, GFX9_3DSTATE_WM, wm) { + wm.BarycentricInterpolationMode = GFX9_BIM_PERSPECTIVE_PIXEL; + } - if (fast_clear) - intel_bb_out(ibb, 1 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); - else - intel_bb_out(ibb, 1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT | - 2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); - - intel_bb_out(ibb, 0); /* scratch space stuff */ - intel_bb_out(ibb, 0); /* scratch hi */ - intel_bb_out(ibb, (max_threads - 1) << GEN8_3DSTATE_PS_MAX_THREADS_SHIFT | - GEN6_3DSTATE_WM_16_DISPATCH_ENABLE | - (fast_clear ? GEN8_3DSTATE_FAST_CLEAR_ENABLE : 0)); - if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) - intel_bb_out(ibb, 6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT | - GENXE_KERNEL0_POLY_PACK16_FIXED << GENXE_KERNEL0_PACKING_POLICY); - else - intel_bb_out(ibb, 6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT); - intel_bb_out(ibb, 0); // kernel 1 - intel_bb_out(ibb, 0); /* kernel 1 hi */ - intel_bb_out(ibb, 0); // kernel 2 - intel_bb_out(ibb, 0); /* kernel 2 hi */ + igt_genxml_emit(ibb, GFX9_3DSTATE_CONSTANT_PS, cps) { + cps.MOCS = intel_get_wb_mocs_index(ibb->fd); + } - intel_bb_out(ibb, GEN8_3DSTATE_PS_BLEND | (2 - 2)); - intel_bb_out(ibb, GEN8_PS_BLEND_HAS_WRITEABLE_RT); + if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) { + igt_genxml_emit(ibb, GFX20_3DSTATE_PS, ps) { + ps.KernelStartPointer0 = kernel; + ps.Kernel0Enable = true; + ps.BindingTableEntryCount = fast_clear ? 1 : 2; + ps.SamplerCount = fast_clear ? 0 : 1; + ps.Kernel0SIMDWidth = GFX20_PS_SIMD16; + ps.RenderTargetFastClearEnable = fast_clear; + ps.MaximumNumberofThreadsPerPSD = max_threads - 1; + ps.DispatchGRFStartRegisterForConstantSetupData0 = 6; + ps.Kernel0PolyPackingPolicy = GFX20_POLY_PACK16_FIXED; + } + } else { + igt_genxml_emit(ibb, GFX9_3DSTATE_PS, ps) { + ps.KernelStartPointer0 = kernel; + ps.BindingTableEntryCount = fast_clear ? 1 : 2; + ps.SamplerCount = fast_clear ? 0 : 1; + ps._16PixelDispatchEnable = true; + ps.RenderTargetFastClearEnable = fast_clear; + ps.MaximumNumberofThreadsPerPSD = max_threads - 1; + ps.DispatchGRFStartRegisterForConstantSetupData0 = 6; + } + } + + igt_genxml_emit(ibb, GFX9_3DSTATE_PS_BLEND, blend) { + blend.HasWriteableRT = true; + } - intel_bb_out(ibb, GEN8_3DSTATE_PS_EXTRA | (2 - 2)); - intel_bb_out(ibb, GEN8_PSX_PIXEL_SHADER_VALID | GEN8_PSX_ATTRIBUTE_ENABLE); + if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) { + igt_genxml_emit(ibb, GFX20_3DSTATE_PS_EXTRA, extra) { + extra.PixelShaderValid = true; + } + } else { + igt_genxml_emit(ibb, GFX9_3DSTATE_PS_EXTRA, extra) { + extra.PixelShaderValid = true; + extra.AttributeEnable = true; + } + } } static void gen9_emit_depth(struct intel_bb *ibb) { - bool need_10dw = HAS_4TILE(ibb->devid); - - intel_bb_out(ibb, GEN8_3DSTATE_WM_DEPTH_STENCIL | (4 - 2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN7_3DSTATE_DEPTH_BUFFER | (need_10dw ? (10-2) : (8-2))); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - if (need_10dw) { - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); + uint8_t mocs = intel_get_wb_mocs_index(ibb->fd); + + igt_genxml_emit(ibb, GFX9_3DSTATE_WM_DEPTH_STENCIL, wds) { } + + if (HAS_4TILE(ibb->devid)) { + igt_genxml_emit(ibb, GFX125_3DSTATE_DEPTH_BUFFER, db) { + db.MOCS = mocs; + } + } else { + igt_genxml_emit(ibb, GFX9_3DSTATE_DEPTH_BUFFER, db) { + db.MOCS = mocs; + } } - intel_bb_out(ibb, GEN8_3DSTATE_HIER_DEPTH_BUFFER | (5-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN8_3DSTATE_STENCIL_BUFFER | (5-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_3DSTATE_HIER_DEPTH_BUFFER, hdb) { + hdb.MOCS = mocs; + } + + igt_genxml_emit(ibb, GFX9_3DSTATE_STENCIL_BUFFER, sb) { + sb.MOCS = mocs; + } } static void @@ -1073,46 +1051,45 @@ gen7_emit_clear(struct intel_bb *ibb) { if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) return; - intel_bb_out(ibb, GEN7_3DSTATE_CLEAR_PARAMS | (3-2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 1); // clear valid + igt_genxml_emit(ibb, GFX9_3DSTATE_CLEAR_PARAMS, cp) { + cp.DepthClearValueValid = true; + } } static void gen6_emit_drawing_rectangle(struct intel_bb *ibb, const struct intel_buf *dst) { - if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) - intel_bb_out(ibb, GENXE2_3DSTATE_DRAWING_RECTANGLE_FAST | (4 - 2)); - else - intel_bb_out(ibb, GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, (intel_buf_height(dst) - 1) << 16 | (intel_buf_width(dst) - 1)); - intel_bb_out(ibb, 0); + if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) { + igt_genxml_emit(ibb, GFX20_3DSTATE_DRAWING_RECTANGLE_FAST, dr) { + dr.ClippedDrawingRectangleXMax = intel_buf_width(dst) - 1; + dr.ClippedDrawingRectangleYMax = intel_buf_height(dst) - 1; + } + } else { + igt_genxml_emit(ibb, GFX9_3DSTATE_DRAWING_RECTANGLE, dr) { + dr.ClippedDrawingRectangleXMax = intel_buf_width(dst) - 1; + dr.ClippedDrawingRectangleYMax = intel_buf_height(dst) - 1; + } + } } static void gen8_emit_vf_topology(struct intel_bb *ibb) { - intel_bb_out(ibb, GEN8_3DSTATE_VF_TOPOLOGY); - intel_bb_out(ibb, _3DPRIM_RECTLIST); + igt_genxml_emit(ibb, GFX9_3DSTATE_VF_TOPOLOGY, vft) { + vft.PrimitiveTopologyType = GFX9_3DPRIM_RECTLIST; + } } /* Vertex elements MUST be defined before this according to spec */ static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset) { - intel_bb_out(ibb, GEN8_3DSTATE_VF | (2 - 2)); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN8_3DSTATE_VF_INSTANCING | (3 - 2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - - intel_bb_out(ibb, GEN4_3DPRIMITIVE | (7-2)); - intel_bb_out(ibb, 0); /* gen8+ ignore the topology type field */ - intel_bb_out(ibb, 3); /* vertex count */ - intel_bb_out(ibb, 0); /* We're specifying this instead with offset in GEN6_3DSTATE_VERTEX_BUFFERS */ - intel_bb_out(ibb, 1); /* single instance */ - intel_bb_out(ibb, 0); /* start instance location */ - intel_bb_out(ibb, 0); /* index buffer offset, ignored */ + igt_genxml_emit(ibb, GFX9_3DSTATE_VF, vf) { } + + igt_genxml_emit(ibb, GFX9_3DSTATE_VF_INSTANCING, vfi) { } + + igt_genxml_emit(ibb, GFX9_3DPRIMITIVE, prim) { + prim.VertexCountPerInstance = 3; + prim.InstanceCount = 1; + } } #define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12) @@ -1244,8 +1221,13 @@ void _gen9_render_op(struct intel_bb *ibb, /* Start emitting the commands. The order roughly follows the mesa blorp * order */ - intel_bb_out(ibb, G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D | - GEN9_PIPELINE_SELECTION_MASK); + igt_genxml_emit(ibb, GFX9_PIPELINE_SELECT, ps) { + ps.PipelineSelection = GFX9_3D; + /* MaskBits 15:8 is a write-enable mask for bits 5:4 (Force Media + * Awake and Media Sampler DOP Clock Gate Enable). Value 0x3 + * enables writes to both bits so PipelineSelection takes effect. */ + ps.MaskBits = 3; + } gen12_emit_aux_pgtable_state(ibb, aux_pgtable_state, true); @@ -1276,17 +1258,21 @@ void _gen9_render_op(struct intel_bb *ibb, gen9_emit_state_base_address(ibb); if (HAS_4TILE(ibb->devid) || intel_gen(ibb->devid) > 12) { - intel_bb_out(ibb, GEN4_3DSTATE_BINDING_TABLE_POOL_ALLOC | 2); - intel_bb_emit_reloc(ibb, ibb->handle, - I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, - 0, ibb->batch_offset); - intel_bb_out(ibb, 1 << 12); + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC, btpa) { + btpa.MOCS = intel_get_wb_mocs_index(ibb->fd); + btpa.BindingTablePoolBaseAddress = + igt_address_of_batch(ibb, + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0); + btpa.BindingTablePoolBufferSize = 1; + } } - intel_bb_out(ibb, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC); - intel_bb_out(ibb, viewport.cc_state); - intel_bb_out(ibb, GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP); - intel_bb_out(ibb, viewport.sf_clip_state); + igt_genxml_emit(ibb, GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC, vp) { + vp.CCViewportPointer = viewport.cc_state; + } + igt_genxml_emit(ibb, GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, vp) { + vp.SFClipViewportPointer = viewport.sf_clip_state; + } gen7_emit_urb(ibb); @@ -1296,11 +1282,7 @@ void _gen9_render_op(struct intel_bb *ibb, gen8_emit_null_state(ibb); - intel_bb_out(ibb, GEN7_3DSTATE_STREAMOUT | (5 - 2)); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); - intel_bb_out(ibb, 0); + igt_genxml_emit(ibb, GFX9_3DSTATE_STREAMOUT, so) { } gen7_emit_clip(ibb); @@ -1308,14 +1290,17 @@ void _gen9_render_op(struct intel_bb *ibb, gen8_emit_ps(ibb, ps_kernel_off, fast_clear); - intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS); - intel_bb_out(ibb, ps_binding_table); + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS, bt) { + bt.PointertoPSBindingTable = ps_binding_table; + } - intel_bb_out(ibb, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS); - intel_bb_out(ibb, ps_sampler_state); + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS, sp) { + sp.PointertoPSSamplerState = ps_sampler_state; + } - intel_bb_out(ibb, GEN8_3DSTATE_SCISSOR_STATE_POINTERS); - intel_bb_out(ibb, scissor_state); + igt_genxml_emit(ibb, GFX9_3DSTATE_SCISSOR_STATE_POINTERS, ssp) { + ssp.ScissorRectPointer = scissor_state; + } gen9_emit_depth(ibb); -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] lib/rendercopy: Convert rendercopy_gen9 to use genxml pack headers 2026-04-07 13:26 ` [PATCH 2/3] lib/rendercopy: Convert rendercopy_gen9 to use genxml pack headers Jan Maslak @ 2026-04-07 15:00 ` Ville Syrjälä 0 siblings, 0 replies; 9+ messages in thread From: Ville Syrjälä @ 2026-04-07 15:00 UTC (permalink / raw) To: Jan Maslak; +Cc: igt-dev, zbigniew.kempczynski On Tue, Apr 07, 2026 at 03:26:19PM +0200, Jan Maslak wrote: > Replace hand-written struct assignments and intel_bb_out() calls in > rendercopy_gen9.c with igt_genxml_emit and igt_genxml_pack_state calls > backed by the genxml pack headers. Command emission is now driven directly > from the hardware XML definitions rather than manually maintained structs. > > Signed-off-by: Jan Maslak <jan.maslak@intel.com> > --- > lib/rendercopy_gen9.c | 1117 ++++++++++++++++++++--------------------- > 1 file changed, 551 insertions(+), 566 deletions(-) > > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c > index d44988010..eecb20a32 100644 > --- a/lib/rendercopy_gen9.c > +++ b/lib/rendercopy_gen9.c > @@ -21,11 +21,17 @@ > #include "intel_io.h" > #include "intel_mocs.h" > #include "rendercopy.h" > -#include "gen9_render.h" > +#include "surfaceformat.h" > #include "xe2_render.h" > #include "intel_reg.h" > #include "igt_aux.h" > #include "intel_chipset.h" > +#include "genxml/igt_genxml.h" > +#include "gen90_pack.h" > +#include "gen110_pack.h" > +#include "gen120_pack.h" > +#include "gen125_pack.h" > +#include "xe2_pack.h" > > #define VERTEX_SIZE (3*4) > > @@ -187,13 +193,60 @@ static uint32_t dg2_compression_format(const struct intel_buf *buf) > } > } > > -/* Mostly copy+paste from gen6, except height, width, pitch moved */ > +/* > + * IGT_RSS_COMMON - set RENDER_SURFACE_STATE fields shared across all gens. > + * Works via C preprocessor structural typing: all gen-specific structs > + * have identical field names for these members. > + */ > +#define IGT_RSS_COMMON(ss, buf, mocs_val, rd, wd) \ > + do { \ > + ss.SurfaceType = GFX9_SURFTYPE_2D; \ > + ss.SurfaceFormat = gen4_surface_format((buf)->bpp, \ > + (buf)->depth); \ > + ss.SurfaceVerticalAlignment = GFX9_VALIGN_4; \ > + ss.MOCS = (mocs_val); \ > + ss.Width = intel_buf_width(buf) - 1; \ > + ss.Height = intel_buf_height(buf) - 1; \ > + ss.SurfacePitch = (buf)->surface[0].stride - 1; \ > + ss.ShaderChannelSelectRed = (int)GFX9_SCS_RED; \ > + ss.ShaderChannelSelectGreen = (int)GFX9_SCS_GREEN; \ > + ss.ShaderChannelSelectBlue = (int)GFX9_SCS_BLUE; \ > + ss.ShaderChannelSelectAlpha = (int)GFX9_SCS_ALPHA; \ > + ss.SurfaceBaseAddress = \ > + igt_address_of((buf), (buf)->surface[0].offset, \ > + (rd), (wd)); \ > + } while (0) > + > +/* > + * IGT_RSS_TILING - set TileMode from buf->tiling. The numeric encoding is > + * identical across gen9/gen12/gen12.5/xe2, but the enum names differ per gen. > + * We use xe2 (GFX20) names as they best reflect the modern tile semantics; > + * (int) casts suppress -Wenum-conversion when used with older-gen structs. > + */ > +#define IGT_RSS_TILING(ss, buf) \ > + do { \ > + switch ((buf)->tiling) { \ > + case I915_TILING_NONE: \ > + ss.TileMode = (int)GFX20_LINEAR; \ > + break; \ > + case I915_TILING_X: \ > + ss.TileMode = (int)GFX20_XMAJOR; \ > + break; \ > + case I915_TILING_64: \ > + ss.TileMode = (int)GFX20_TILE64; \ > + ss.MipTailStartLOD = 0xf; \ > + break; \ > + default: \ > + ss.TileMode = (int)GFX20_TILE4; \ > + } \ > + } while (0) > + > static uint32_t > -gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst, > - bool fast_clear) { > - struct gen9_surface_state *ss; > +gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) { > uint32_t write_domain, read_domain; > - uint64_t address; > + unsigned int gen = intel_gen(ibb->devid); > + uint32_t mocs; > + void *ss_ptr; > > igt_assert_lte(buf->surface[0].stride, 256*1024); > igt_assert_lte(intel_buf_width(buf), 16384); > @@ -206,120 +259,106 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst, > read_domain = I915_GEM_DOMAIN_SAMPLER; > } > > - ss = intel_bb_ptr_align(ibb, 64); > - > - ss->ss0.surface_type = SURFACE_2D; > - ss->ss0.surface_format = gen4_surface_format(buf->bpp, buf->depth); > - ss->ss0.vertical_alignment = 1; /* align 4 */ > - ss->ss0.horizontal_alignment = 1; /* align 4 or HALIGN_32 on display ver >= 13*/ > + /* MOCS encoding: genxml has a single 7-bit MOCS field (bits 30:24). > + * The old struct had mocs_index:6 at bits 30:25 and pxp:1 at bit 24. > + * Reproduce the same bit layout. */ > + mocs = (buf->mocs_index << 1) | (intel_buf_pxp(buf) ? 1 : 0); This annoying mocs_index stuff should be nuked throughout igt, and replaced with the full mocs field. I've already gotten confused by this multiple times when it looked like the relevant macros were off by one bit when compared to the spec. <snip> > static void gen7_emit_vertex_buffer(struct intel_bb *ibb, uint32_t offset) > { > - intel_bb_out(ibb, GEN4_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2)); > - intel_bb_out(ibb, 0 << GEN6_VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */ > - GEN8_VB0_BUFFER_ADDR_MOD_EN | /* Address Modify Enable */ > - VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT); > - intel_bb_emit_reloc(ibb, ibb->handle, > - I915_GEM_DOMAIN_VERTEX, 0, > - offset, ibb->batch_offset); > - intel_bb_out(ibb, 3 * VERTEX_SIZE); > + void *vb_ptr; > + > + /* Variable-length: 1 header dword + VERTEX_BUFFER_STATE element */ > + { > + struct GFX9_3DSTATE_VERTEX_BUFFERS vbs = { GFX9_3DSTATE_VERTEX_BUFFERS_header }; > + /* Default DWordLength=3 is correct for 1 element (1 + 4 - 2 = 3) */ > + GFX9_3DSTATE_VERTEX_BUFFERS_pack(ibb, intel_bb_ptr(ibb), &vbs); > + intel_bb_ptr_add(ibb, 4); > + } > + > + vb_ptr = intel_bb_ptr(ibb); > + igt_genxml_pack_state(ibb, GFX9_VERTEX_BUFFER_STATE, vb_ptr, vb) { > + vb.VertexBufferIndex = 0; > + vb.AddressModifyEnable = true; > + vb.MOCS = intel_get_wb_mocs_index(ibb->fd); Where did this come from, and why doesn't it have the <<1 ? The patch is rather big so little things can easily get lost in the noise. Is it possible to do the conversion to genxml in pieces (maybe one packet per patch)? > + vb.BufferPitch = VERTEX_SIZE; > + vb.BufferStartingAddress = (struct igt_address){ > + .offset = ibb->batch_offset + offset, > + .handle = ibb->handle, > + .read_domains = I915_GEM_DOMAIN_VERTEX, > + .write_domain = 0, > + .presumed_offset = ibb->batch_offset, > + }; > + vb.BufferSize = 3 * VERTEX_SIZE; > + } > + intel_bb_ptr_add(ibb, GFX9_VERTEX_BUFFER_STATE_length * 4); > } > > static uint32_t > gen6_create_cc_state(struct intel_bb *ibb) > { > - struct gen6_color_calc_state *cc_state; > + void *ptr = intel_bb_ptr_align(ibb, 64); > > - cc_state = intel_bb_ptr_align(ibb, 64); > + igt_genxml_pack_state(ibb, GFX9_COLOR_CALC_STATE, ptr, cc_state) { } > > - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*cc_state)); > + return intel_bb_ptr_add_return_prev_offset(ibb, > + GFX9_COLOR_CALC_STATE_length * 4); > } > > static uint32_t > gen8_create_blend_state(struct intel_bb *ibb) > { > - struct gen8_blend_state *blend; > - int i; > - > - blend = intel_bb_ptr_align(ibb, 64); > - > - for (i = 0; i < 16; i++) { > - blend->bs[i].dest_blend_factor = GEN6_BLENDFACTOR_ZERO; > - blend->bs[i].source_blend_factor = GEN6_BLENDFACTOR_ONE; > - blend->bs[i].color_blend_func = GEN6_BLENDFUNCTION_ADD; > - blend->bs[i].pre_blend_color_clamp = 1; > - blend->bs[i].color_buffer_blend = 0; > + void *ptr = intel_bb_ptr_align(ibb, 64); > + > + /* Blend state header (1 dword) - all defaults (zeros) */ > + igt_genxml_pack_state(ibb, GFX9_BLEND_STATE, ptr, bs) { } > + ptr += GFX9_BLEND_STATE_length * 4; > + > + /* 16 per-RT blend state entries */ > + for (int i = 0; i < 16; i++) { > + igt_genxml_pack_state(ibb, GFX9_BLEND_STATE_ENTRY, ptr, entry) { > + entry.DestinationBlendFactor = GFX9_BLENDFACTOR_ZERO; > + entry.SourceBlendFactor = GFX9_BLENDFACTOR_ONE; > + entry.ColorBlendFunction = GFX9_BLENDFUNCTION_ADD; > + entry.PreBlendColorClampEnable = true; > + } > + ptr += GFX9_BLEND_STATE_ENTRY_length * 4; > } > > - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*blend)); > + return intel_bb_ptr_add_return_prev_offset(ibb, > + (GFX9_BLEND_STATE_length + 16 * GFX9_BLEND_STATE_ENTRY_length) * 4); > } > > static uint32_t > gen6_create_cc_viewport(struct intel_bb *ibb) > { > - struct gen4_cc_viewport *vp; > - > - vp = intel_bb_ptr_align(ibb, 32); > + void *ptr = intel_bb_ptr_align(ibb, 32); > > - /* XXX I don't understand this */ > - vp->min_depth = -1.e35; > - vp->max_depth = 1.e35; > + igt_genxml_pack_state(ibb, GFX9_CC_VIEWPORT, ptr, vp) { > + vp.MinimumDepth = -1.e35; > + vp.MaximumDepth = 1.e35; > + } > > - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*vp)); > + return intel_bb_ptr_add_return_prev_offset(ibb, > + GFX9_CC_VIEWPORT_length * 4); > } > > static uint32_t > gen7_create_sf_clip_viewport(struct intel_bb *ibb) { > - /* XXX these are likely not needed */ > - struct gen7_sf_clip_viewport *scv_state; > - > - scv_state = intel_bb_ptr_align(ibb, 64); > + void *ptr = intel_bb_ptr_align(ibb, 64); > > - scv_state->guardband.xmin = 0; > - scv_state->guardband.xmax = 1.0f; > - scv_state->guardband.ymin = 0; > - scv_state->guardband.ymax = 1.0f; > + igt_genxml_pack_state(ibb, GFX9_SF_CLIP_VIEWPORT, ptr, scv) { > + scv.XMinClipGuardband = 0; > + scv.XMaxClipGuardband = 1.0f; > + scv.YMinClipGuardband = 0; > + scv.YMaxClipGuardband = 1.0f; > + } > > - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*scv_state)); > + return intel_bb_ptr_add_return_prev_offset(ibb, > + GFX9_SF_CLIP_VIEWPORT_length * 4); > } > > static uint32_t > gen6_create_scissor_rect(struct intel_bb *ibb) > { > - struct gen6_scissor_rect *scissor; > + void *ptr = intel_bb_ptr_align(ibb, 64); > > - scissor = intel_bb_ptr_align(ibb, 64); > + igt_genxml_pack_state(ibb, GFX9_SCISSOR_RECT, ptr, sr) { } > > - return intel_bb_ptr_add_return_prev_offset(ibb, sizeof(*scissor)); > + return intel_bb_ptr_add_return_prev_offset(ibb, > + GFX9_SCISSOR_RECT_length * 4); > } > > static void > gen8_emit_sip(struct intel_bb *ibb) { > - intel_bb_out(ibb, GEN4_STATE_SIP | (3 - 2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_STATE_SIP, sip) { > + /* SystemInstructionPointer left as zero */ > + } > } > > static void > gen7_emit_push_constants(struct intel_bb *ibb) { > - intel_bb_out(ibb, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS, vs) { } > + igt_genxml_emit(ibb, GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS, hs) { } > + igt_genxml_emit(ibb, GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS, ds) { } > + igt_genxml_emit(ibb, GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS, gs) { } > + igt_genxml_emit(ibb, GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS, ps) { } > } > > +/* > + * IGT_SBA_COMMON - shared STATE_BASE_ADDRESS fields across gen9/gen11/gen125. > + * All three variants have identical field names for the fields we set. > + */ > +#define IGT_SBA_COMMON(sba, mocs_val, surf, dyn, inst) \ > + do { \ > + sba.GeneralStateBaseAddressModifyEnable = true; \ > + sba.GeneralStateMOCS = (mocs_val); \ > + sba.StatelessDataPortAccessMOCS = (mocs_val); \ > + sba.SurfaceStateBaseAddressModifyEnable = true; \ > + sba.SurfaceStateMOCS = (mocs_val); \ > + sba.SurfaceStateBaseAddress = (surf); \ > + sba.DynamicStateBaseAddressModifyEnable = true; \ > + sba.DynamicStateMOCS = (mocs_val); \ > + sba.DynamicStateBaseAddress = (dyn); \ > + sba.IndirectObjectMOCS = (mocs_val); \ > + sba.InstructionBaseAddressModifyEnable = true; \ > + sba.InstructionMOCS = (mocs_val); \ > + sba.InstructionBaseAddress = (inst); \ > + sba.GeneralStateBufferSizeModifyEnable = true; \ > + sba.GeneralStateBufferSize = 0xfffff; \ > + sba.DynamicStateBufferSizeModifyEnable = true; \ > + sba.DynamicStateBufferSize = 1; \ > + sba.IndirectObjectBufferSizeModifyEnable = true; \ > + sba.IndirectObjectBufferSize = 0xfffff; \ > + sba.InstructionBuffersizeModifyEnable = true; \ > + sba.InstructionBufferSize = 1; \ > + sba.BindlessSurfaceStateMOCS = (mocs_val); \ > + } while (0) > + > static void > gen9_emit_state_base_address(struct intel_bb *ibb) { > + uint8_t mocs = intel_get_wb_mocs_index(ibb->fd); > > - /* WaBindlessSurfaceStateModifyEnable:skl,bxt */ > - /* The length has to be one less if we dont modify > - bindless state */ > - if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) > - intel_bb_out(ibb, GEN4_STATE_BASE_ADDRESS | 20); > - else > - intel_bb_out(ibb, GEN4_STATE_BASE_ADDRESS | (19 - 1 - 2)); > - > - /* general */ > - intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); > - intel_bb_out(ibb, 0); > - > - /* stateless data port */ > - intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY); > - > - /* surface */ > - intel_bb_emit_reloc(ibb, ibb->handle, > - I915_GEM_DOMAIN_SAMPLER, 0, > - BASE_ADDRESS_MODIFY, ibb->batch_offset); > - > - /* dynamic */ > - intel_bb_emit_reloc(ibb, ibb->handle, > - I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, > - BASE_ADDRESS_MODIFY, ibb->batch_offset); > - > - /* indirect */ > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - /* instruction */ > - intel_bb_emit_reloc(ibb, ibb->handle, > - I915_GEM_DOMAIN_INSTRUCTION, 0, > - BASE_ADDRESS_MODIFY, ibb->batch_offset); > - > - /* general state buffer size */ > - intel_bb_out(ibb, 0xfffff000 | 1); > - /* dynamic state buffer size */ > - intel_bb_out(ibb, 1 << 12 | 1); > - /* indirect object buffer size */ > - intel_bb_out(ibb, 0xfffff000 | 1); > - /* intruction buffer size */ > - intel_bb_out(ibb, 1 << 12 | 1); > - > - /* Bindless surface state base address */ > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > + struct igt_address surf_base = > + igt_address_of_batch(ibb, I915_GEM_DOMAIN_SAMPLER, 0); > + struct igt_address dyn_base = > + igt_address_of_batch(ibb, > + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0); > + struct igt_address inst_base = > + igt_address_of_batch(ibb, I915_GEM_DOMAIN_INSTRUCTION, 0); > > - if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) { > - /* Bindless sampler */ > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > + if (HAS_4TILE(ibb->devid) || intel_gen(ibb->devid) > 12) { > + igt_genxml_emit(ibb, GFX125_STATE_BASE_ADDRESS, sba) { > + IGT_SBA_COMMON(sba, mocs, surf_base, dyn_base, inst_base); > + /* WBP (0) and UC (1) are marked dont_use in the XML for this field. */ > + sba.L1CacheControl = GFX125_L1CC_WB; > + sba.BindlessSamplerStateBaseAddressModifyEnable = true; > + sba.BindlessSamplerStateMOCS = mocs; > + } > + } else if (intel_gen(ibb->devid) >= 11) { > + igt_genxml_emit(ibb, GFX11_STATE_BASE_ADDRESS, sba) { > + IGT_SBA_COMMON(sba, mocs, surf_base, dyn_base, inst_base); > + sba.BindlessSamplerStateBaseAddressModifyEnable = true; > + sba.BindlessSamplerStateMOCS = mocs; > + } > + } else { > + igt_genxml_emit(ibb, GFX9_STATE_BASE_ADDRESS, sba) { > + IGT_SBA_COMMON(sba, mocs, surf_base, dyn_base, inst_base); > + } > } > } > > @@ -750,184 +821,119 @@ gen7_emit_urb(struct intel_bb *ibb) { > const int vs_size = 2; > const int vs_start = 4; > > - intel_bb_out(ibb, GEN7_3DSTATE_URB_VS); > - intel_bb_out(ibb, vs_entries | ((vs_size - 1) << 16) | (vs_start << 25)); > - intel_bb_out(ibb, GEN7_3DSTATE_URB_GS); > - intel_bb_out(ibb, vs_start << 25); > - intel_bb_out(ibb, GEN7_3DSTATE_URB_HS); > - intel_bb_out(ibb, vs_start << 25); > - intel_bb_out(ibb, GEN7_3DSTATE_URB_DS); > - intel_bb_out(ibb, vs_start << 25); > + igt_genxml_emit(ibb, GFX9_3DSTATE_URB_VS, urb) { > + urb.VSNumberofURBEntries = vs_entries; > + urb.VSURBEntryAllocationSize = vs_size - 1; > + urb.VSURBStartingAddress = vs_start; > + } > + igt_genxml_emit(ibb, GFX9_3DSTATE_URB_GS, urb) { > + urb.GSURBStartingAddress = vs_start; > + } > + igt_genxml_emit(ibb, GFX9_3DSTATE_URB_HS, urb) { > + urb.HSURBStartingAddress = vs_start; > + } > + igt_genxml_emit(ibb, GFX9_3DSTATE_URB_DS, urb) { > + urb.DSURBStartingAddress = vs_start; > + } > } > > static void > gen8_emit_cc(struct intel_bb *ibb) { > - intel_bb_out(ibb, GEN7_3DSTATE_BLEND_STATE_POINTERS); > - intel_bb_out(ibb, cc.blend_state | 1); > + igt_genxml_emit(ibb, GFX9_3DSTATE_BLEND_STATE_POINTERS, bsp) { > + bsp.BlendStatePointer = cc.blend_state; > + bsp.BlendStatePointerValid = true; > + } > > - intel_bb_out(ibb, GEN6_3DSTATE_CC_STATE_POINTERS); > - intel_bb_out(ibb, cc.cc_state | 1); > + igt_genxml_emit(ibb, GFX9_3DSTATE_CC_STATE_POINTERS, ccp) { > + ccp.ColorCalcStatePointer = cc.cc_state; > + ccp.ColorCalcStatePointerValid = true; > + } > } > > static void > gen8_emit_multisample(struct intel_bb *ibb) { > - intel_bb_out(ibb, GEN8_3DSTATE_MULTISAMPLE | 0); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_3DSTATE_MULTISAMPLE, ms) { } > > - intel_bb_out(ibb, GEN6_3DSTATE_SAMPLE_MASK); > - intel_bb_out(ibb, 1); > + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLE_MASK, sm) { > + sm.SampleMask = 1; > + } > } > > static void > gen8_emit_vs(struct intel_bb *ibb) { > - intel_bb_out(ibb, GEN6_3DSTATE_CONSTANT_VS | (11-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN6_3DSTATE_VS | (9-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_3DSTATE_CONSTANT_VS, cvs) { > + cvs.MOCS = intel_get_wb_mocs_index(ibb->fd); > + } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS, bt) { } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS, sp) { } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_VS, vs) { } > } > > static void > gen8_emit_hs(struct intel_bb *ibb) { > - intel_bb_out(ibb, GEN7_3DSTATE_CONSTANT_HS | (11-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN7_3DSTATE_HS | (9-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_3DSTATE_CONSTANT_HS, chs) { > + chs.MOCS = intel_get_wb_mocs_index(ibb->fd); > + } > + > + if (intel_gen(ibb->devid) >= 20) > + igt_genxml_emit(ibb, GFX20_3DSTATE_HS, hs) { } > + else > + igt_genxml_emit(ibb, GFX9_3DSTATE_HS, hs) { } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS, bt) { } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS, sp) { } > } > > static void > gen8_emit_gs(struct intel_bb *ibb) { > - intel_bb_out(ibb, GEN6_3DSTATE_CONSTANT_GS | (11-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN6_3DSTATE_GS | (10-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_3DSTATE_CONSTANT_GS, cgs) { > + cgs.MOCS = intel_get_wb_mocs_index(ibb->fd); > + } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_GS, gs) { } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS, bt) { } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS, sp) { } > } > > static void > gen9_emit_ds(struct intel_bb *ibb) { > - intel_bb_out(ibb, GEN7_3DSTATE_CONSTANT_DS | (11-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN7_3DSTATE_DS | (11-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_3DSTATE_CONSTANT_DS, cds) { > + cds.MOCS = intel_get_wb_mocs_index(ibb->fd); > + } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_DS, ds) { } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS, bt) { } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS, sp) { } > } > > > static void > gen8_emit_wm_hz_op(struct intel_bb *ibb) { > if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) { > - intel_bb_out(ibb, GEN8_3DSTATE_WM_HZ_OP | (6-2)); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX20_3DSTATE_WM_HZ_OP, hz) { } > } else { > - intel_bb_out(ibb, GEN8_3DSTATE_WM_HZ_OP | (5-2)); > + igt_genxml_emit(ibb, GFX9_3DSTATE_WM_HZ_OP, hz) { } > } > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > } > > static void > gen8_emit_null_state(struct intel_bb *ibb) { > gen8_emit_wm_hz_op(ibb); > gen8_emit_hs(ibb); > - intel_bb_out(ibb, GEN7_3DSTATE_TE | (4-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > + > + if (intel_gen(ibb->devid) >= 12) > + igt_genxml_emit(ibb, GFX12_3DSTATE_TE, te) { } > + else > + igt_genxml_emit(ibb, GFX9_3DSTATE_TE, te) { } > + > gen8_emit_gs(ibb); > gen9_emit_ds(ibb); > gen8_emit_vs(ibb); > @@ -935,137 +941,109 @@ gen8_emit_null_state(struct intel_bb *ibb) { > > static void > gen7_emit_clip(struct intel_bb *ibb) { > - intel_bb_out(ibb, GEN6_3DSTATE_CLIP | (4 - 2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); /* pass-through */ > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_3DSTATE_CLIP, clip) { > + /* All fields zero = pass-through */ > + } > } > > static void > gen8_emit_sf(struct intel_bb *ibb) > { > - int i; > - > - intel_bb_out(ibb, GEN7_3DSTATE_SBE | (6 - 2)); > - intel_bb_out(ibb, 1 << GEN7_SBE_NUM_OUTPUTS_SHIFT | > - GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH | > - GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET | > - 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT | > - 1 << GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, GEN9_SBE_ACTIVE_COMPONENT_XYZW << 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN8_3DSTATE_SBE_SWIZ | (11 - 2)); > - for (i = 0; i < 8; i++) > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN8_3DSTATE_RASTER | (5 - 2)); > - intel_bb_out(ibb, GEN8_RASTER_FRONT_WINDING_CCW | GEN8_RASTER_CULL_NONE); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN6_3DSTATE_SF | (4 - 2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_3DSTATE_SBE, sbe) { > + sbe.NumberofSFOutputAttributes = 1; > + sbe.ForceVertexURBEntryReadLength = true; > + sbe.ForceVertexURBEntryReadOffset = true; > + sbe.VertexURBEntryReadLength = 1; > + sbe.VertexURBEntryReadOffset = 1; > + sbe.AttributeActiveComponentFormat[0] = GFX9_ACTIVE_COMPONENT_XYZW; > + } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_SBE_SWIZ, swiz) { } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_RASTER, raster) { > + raster.FrontWinding = 1; /* CCW */ > + raster.CullMode = GFX9_CULLMODE_NONE; > + } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_SF, sf) { } > } > > static void > gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel, bool fast_clear) { > const int max_threads = 63; > > - intel_bb_out(ibb, GEN6_3DSTATE_WM | (2 - 2)); > - intel_bb_out(ibb, /* XXX: I don't understand the BARYCENTRIC stuff, but it > - * appears we need it to put our setup data in the place we > - * expect (g6, see below) */ > - GEN8_3DSTATE_PS_PERSPECTIVE_PIXEL_BARYCENTRIC); > - > - intel_bb_out(ibb, GEN6_3DSTATE_CONSTANT_PS | (11-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN7_3DSTATE_PS | (12-2)); > - if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) > - intel_bb_out(ibb, kernel | 1); > - else > - intel_bb_out(ibb, kernel); > - intel_bb_out(ibb, 0); /* kernel hi */ > + igt_genxml_emit(ibb, GFX9_3DSTATE_WM, wm) { > + wm.BarycentricInterpolationMode = GFX9_BIM_PERSPECTIVE_PIXEL; > + } > > - if (fast_clear) > - intel_bb_out(ibb, 1 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); > - else > - intel_bb_out(ibb, 1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT | > - 2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); > - > - intel_bb_out(ibb, 0); /* scratch space stuff */ > - intel_bb_out(ibb, 0); /* scratch hi */ > - intel_bb_out(ibb, (max_threads - 1) << GEN8_3DSTATE_PS_MAX_THREADS_SHIFT | > - GEN6_3DSTATE_WM_16_DISPATCH_ENABLE | > - (fast_clear ? GEN8_3DSTATE_FAST_CLEAR_ENABLE : 0)); > - if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) > - intel_bb_out(ibb, 6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT | > - GENXE_KERNEL0_POLY_PACK16_FIXED << GENXE_KERNEL0_PACKING_POLICY); > - else > - intel_bb_out(ibb, 6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT); > - intel_bb_out(ibb, 0); // kernel 1 > - intel_bb_out(ibb, 0); /* kernel 1 hi */ > - intel_bb_out(ibb, 0); // kernel 2 > - intel_bb_out(ibb, 0); /* kernel 2 hi */ > + igt_genxml_emit(ibb, GFX9_3DSTATE_CONSTANT_PS, cps) { > + cps.MOCS = intel_get_wb_mocs_index(ibb->fd); > + } > > - intel_bb_out(ibb, GEN8_3DSTATE_PS_BLEND | (2 - 2)); > - intel_bb_out(ibb, GEN8_PS_BLEND_HAS_WRITEABLE_RT); > + if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) { > + igt_genxml_emit(ibb, GFX20_3DSTATE_PS, ps) { > + ps.KernelStartPointer0 = kernel; > + ps.Kernel0Enable = true; > + ps.BindingTableEntryCount = fast_clear ? 1 : 2; > + ps.SamplerCount = fast_clear ? 0 : 1; > + ps.Kernel0SIMDWidth = GFX20_PS_SIMD16; > + ps.RenderTargetFastClearEnable = fast_clear; > + ps.MaximumNumberofThreadsPerPSD = max_threads - 1; > + ps.DispatchGRFStartRegisterForConstantSetupData0 = 6; > + ps.Kernel0PolyPackingPolicy = GFX20_POLY_PACK16_FIXED; > + } > + } else { > + igt_genxml_emit(ibb, GFX9_3DSTATE_PS, ps) { > + ps.KernelStartPointer0 = kernel; > + ps.BindingTableEntryCount = fast_clear ? 1 : 2; > + ps.SamplerCount = fast_clear ? 0 : 1; > + ps._16PixelDispatchEnable = true; > + ps.RenderTargetFastClearEnable = fast_clear; > + ps.MaximumNumberofThreadsPerPSD = max_threads - 1; > + ps.DispatchGRFStartRegisterForConstantSetupData0 = 6; > + } > + } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_PS_BLEND, blend) { > + blend.HasWriteableRT = true; > + } > > - intel_bb_out(ibb, GEN8_3DSTATE_PS_EXTRA | (2 - 2)); > - intel_bb_out(ibb, GEN8_PSX_PIXEL_SHADER_VALID | GEN8_PSX_ATTRIBUTE_ENABLE); > + if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) { > + igt_genxml_emit(ibb, GFX20_3DSTATE_PS_EXTRA, extra) { > + extra.PixelShaderValid = true; > + } > + } else { > + igt_genxml_emit(ibb, GFX9_3DSTATE_PS_EXTRA, extra) { > + extra.PixelShaderValid = true; > + extra.AttributeEnable = true; > + } > + } > } > > static void > gen9_emit_depth(struct intel_bb *ibb) > { > - bool need_10dw = HAS_4TILE(ibb->devid); > - > - intel_bb_out(ibb, GEN8_3DSTATE_WM_DEPTH_STENCIL | (4 - 2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN7_3DSTATE_DEPTH_BUFFER | (need_10dw ? (10-2) : (8-2))); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - if (need_10dw) { > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > + uint8_t mocs = intel_get_wb_mocs_index(ibb->fd); > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_WM_DEPTH_STENCIL, wds) { } > + > + if (HAS_4TILE(ibb->devid)) { > + igt_genxml_emit(ibb, GFX125_3DSTATE_DEPTH_BUFFER, db) { > + db.MOCS = mocs; > + } > + } else { > + igt_genxml_emit(ibb, GFX9_3DSTATE_DEPTH_BUFFER, db) { > + db.MOCS = mocs; > + } > } > > - intel_bb_out(ibb, GEN8_3DSTATE_HIER_DEPTH_BUFFER | (5-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN8_3DSTATE_STENCIL_BUFFER | (5-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_3DSTATE_HIER_DEPTH_BUFFER, hdb) { > + hdb.MOCS = mocs; > + } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_STENCIL_BUFFER, sb) { > + sb.MOCS = mocs; > + } > } > > static void > @@ -1073,46 +1051,45 @@ gen7_emit_clear(struct intel_bb *ibb) { > if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) > return; > > - intel_bb_out(ibb, GEN7_3DSTATE_CLEAR_PARAMS | (3-2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 1); // clear valid > + igt_genxml_emit(ibb, GFX9_3DSTATE_CLEAR_PARAMS, cp) { > + cp.DepthClearValueValid = true; > + } > } > > static void > gen6_emit_drawing_rectangle(struct intel_bb *ibb, const struct intel_buf *dst) > { > - if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) > - intel_bb_out(ibb, GENXE2_3DSTATE_DRAWING_RECTANGLE_FAST | (4 - 2)); > - else > - intel_bb_out(ibb, GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, (intel_buf_height(dst) - 1) << 16 | (intel_buf_width(dst) - 1)); > - intel_bb_out(ibb, 0); > + if (intel_gen(intel_get_drm_devid(ibb->fd)) >= 20) { > + igt_genxml_emit(ibb, GFX20_3DSTATE_DRAWING_RECTANGLE_FAST, dr) { > + dr.ClippedDrawingRectangleXMax = intel_buf_width(dst) - 1; > + dr.ClippedDrawingRectangleYMax = intel_buf_height(dst) - 1; > + } > + } else { > + igt_genxml_emit(ibb, GFX9_3DSTATE_DRAWING_RECTANGLE, dr) { > + dr.ClippedDrawingRectangleXMax = intel_buf_width(dst) - 1; > + dr.ClippedDrawingRectangleYMax = intel_buf_height(dst) - 1; > + } > + } > } > > static void gen8_emit_vf_topology(struct intel_bb *ibb) > { > - intel_bb_out(ibb, GEN8_3DSTATE_VF_TOPOLOGY); > - intel_bb_out(ibb, _3DPRIM_RECTLIST); > + igt_genxml_emit(ibb, GFX9_3DSTATE_VF_TOPOLOGY, vft) { > + vft.PrimitiveTopologyType = GFX9_3DPRIM_RECTLIST; > + } > } > > /* Vertex elements MUST be defined before this according to spec */ > static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset) > { > - intel_bb_out(ibb, GEN8_3DSTATE_VF | (2 - 2)); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN8_3DSTATE_VF_INSTANCING | (3 - 2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - > - intel_bb_out(ibb, GEN4_3DPRIMITIVE | (7-2)); > - intel_bb_out(ibb, 0); /* gen8+ ignore the topology type field */ > - intel_bb_out(ibb, 3); /* vertex count */ > - intel_bb_out(ibb, 0); /* We're specifying this instead with offset in GEN6_3DSTATE_VERTEX_BUFFERS */ > - intel_bb_out(ibb, 1); /* single instance */ > - intel_bb_out(ibb, 0); /* start instance location */ > - intel_bb_out(ibb, 0); /* index buffer offset, ignored */ > + igt_genxml_emit(ibb, GFX9_3DSTATE_VF, vf) { } > + > + igt_genxml_emit(ibb, GFX9_3DSTATE_VF_INSTANCING, vfi) { } > + > + igt_genxml_emit(ibb, GFX9_3DPRIMITIVE, prim) { > + prim.VertexCountPerInstance = 3; > + prim.InstanceCount = 1; > + } > } > > #define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12) > @@ -1244,8 +1221,13 @@ void _gen9_render_op(struct intel_bb *ibb, > > /* Start emitting the commands. The order roughly follows the mesa blorp > * order */ > - intel_bb_out(ibb, G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D | > - GEN9_PIPELINE_SELECTION_MASK); > + igt_genxml_emit(ibb, GFX9_PIPELINE_SELECT, ps) { > + ps.PipelineSelection = GFX9_3D; > + /* MaskBits 15:8 is a write-enable mask for bits 5:4 (Force Media > + * Awake and Media Sampler DOP Clock Gate Enable). Value 0x3 > + * enables writes to both bits so PipelineSelection takes effect. */ > + ps.MaskBits = 3; > + } > > gen12_emit_aux_pgtable_state(ibb, aux_pgtable_state, true); > > @@ -1276,17 +1258,21 @@ void _gen9_render_op(struct intel_bb *ibb, > gen9_emit_state_base_address(ibb); > > if (HAS_4TILE(ibb->devid) || intel_gen(ibb->devid) > 12) { > - intel_bb_out(ibb, GEN4_3DSTATE_BINDING_TABLE_POOL_ALLOC | 2); > - intel_bb_emit_reloc(ibb, ibb->handle, > - I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, > - 0, ibb->batch_offset); > - intel_bb_out(ibb, 1 << 12); > + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC, btpa) { > + btpa.MOCS = intel_get_wb_mocs_index(ibb->fd); > + btpa.BindingTablePoolBaseAddress = > + igt_address_of_batch(ibb, > + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0); > + btpa.BindingTablePoolBufferSize = 1; > + } > } > > - intel_bb_out(ibb, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC); > - intel_bb_out(ibb, viewport.cc_state); > - intel_bb_out(ibb, GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP); > - intel_bb_out(ibb, viewport.sf_clip_state); > + igt_genxml_emit(ibb, GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC, vp) { > + vp.CCViewportPointer = viewport.cc_state; > + } > + igt_genxml_emit(ibb, GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, vp) { > + vp.SFClipViewportPointer = viewport.sf_clip_state; > + } > > gen7_emit_urb(ibb); > > @@ -1296,11 +1282,7 @@ void _gen9_render_op(struct intel_bb *ibb, > > gen8_emit_null_state(ibb); > > - intel_bb_out(ibb, GEN7_3DSTATE_STREAMOUT | (5 - 2)); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > - intel_bb_out(ibb, 0); > + igt_genxml_emit(ibb, GFX9_3DSTATE_STREAMOUT, so) { } > > gen7_emit_clip(ibb); > > @@ -1308,14 +1290,17 @@ void _gen9_render_op(struct intel_bb *ibb, > > gen8_emit_ps(ibb, ps_kernel_off, fast_clear); > > - intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS); > - intel_bb_out(ibb, ps_binding_table); > + igt_genxml_emit(ibb, GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS, bt) { > + bt.PointertoPSBindingTable = ps_binding_table; > + } > > - intel_bb_out(ibb, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS); > - intel_bb_out(ibb, ps_sampler_state); > + igt_genxml_emit(ibb, GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS, sp) { > + sp.PointertoPSSamplerState = ps_sampler_state; > + } > > - intel_bb_out(ibb, GEN8_3DSTATE_SCISSOR_STATE_POINTERS); > - intel_bb_out(ibb, scissor_state); > + igt_genxml_emit(ibb, GFX9_3DSTATE_SCISSOR_STATE_POINTERS, ssp) { > + ssp.ScissorRectPointer = scissor_state; > + } > > gen9_emit_depth(ibb); > > -- > 2.34.1 -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] lib: Add genxml annotated batch buffer decode 2026-04-07 13:26 [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT Jan Maslak 2026-04-07 13:26 ` [PATCH 2/3] lib/rendercopy: Convert rendercopy_gen9 to use genxml pack headers Jan Maslak @ 2026-04-07 13:26 ` Jan Maslak 2026-04-08 9:23 ` [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT Jani Nikula ` (4 subsequent siblings) 6 siblings, 0 replies; 9+ messages in thread From: Jan Maslak @ 2026-04-07 13:26 UTC (permalink / raw) To: igt-dev; +Cc: zbigniew.kempczynski, Jan Maslak When IGT_BB_ANNOTATE=1 is set, intel_bb_dump() writes a companion <filename>.annotated file alongside the raw hex dump. The annotated file identifies each command and prints its field names and values, decoded via the genxml *_decode.h headers. The opt-in environment variable avoids file I/O overhead in normal test runs. A disclaimer in the file header notes that the decode is best-effort and may lag hardware on newer platforms. Signed-off-by: Jan Maslak <jan.maslak@intel.com> --- lib/intel_batchbuffer.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index b09506574..3d1ee2dab 100644 --- a/lib/intel_batchbuffer.c +++ b/lib/intel_batchbuffer.c @@ -49,6 +49,7 @@ #include "veboxcopy.h" #include "xe/xe_ioctl.h" #include "xe/xe_query.h" +#include "genxml/igt_genxml_decode.h" #define BCS_SWCTRL 0x22200 #define BCS_SRC_Y (1 << 0) @@ -1579,7 +1580,9 @@ void intel_bb_print(struct intel_bb *ibb) * @filename: name to which write bb * @in_hex: dump bb in hex form * - * Dump batch bo to file. + * Dump batch bo to file. When IGT_BB_ANNOTATE=1 is set, also writes + * a companion annotated file (filename + ".annotated") with + * genxml-decoded field names and values. */ void intel_bb_dump(struct intel_bb *ibb, const char *filename, bool in_hex) { @@ -1609,6 +1612,33 @@ void intel_bb_dump(struct intel_bb *ibb, const char *filename, bool in_hex) } fclose(out); + /* Write a companion annotated decode alongside the raw dump, + * but only when explicitly requested via IGT_BB_ANNOTATE=1. + */ + if (getenv("IGT_BB_ANNOTATE")) { + char *ann_filename; + unsigned batch_dwords; + + igt_assert(asprintf(&ann_filename, "%s.annotated", filename) > 0); + batch_dwords = intel_bb_offset(ibb) / sizeof(uint32_t); + + out = fopen(ann_filename, "w"); + if (out) { + fprintf(out, + "# Batch buffer annotated decode\n" + "# Decoded using IGT's genxml definitions.\n" + "# This is a best-effort annotation and may be inaccurate,\n" + "# especially on newer platforms where the XML definitions\n" + "# may not yet reflect the latest hardware changes.\n" + "\n"); + igt_genxml_decode_batch(out, ibb->devid, + (const uint32_t *)ptr, + batch_dwords); + fclose(out); + } + free(ann_filename); + } + if (ptr != ibb->batch) munmap(ptr, ibb->size); } -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT 2026-04-07 13:26 [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT Jan Maslak 2026-04-07 13:26 ` [PATCH 2/3] lib/rendercopy: Convert rendercopy_gen9 to use genxml pack headers Jan Maslak 2026-04-07 13:26 ` [PATCH 3/3] lib: Add genxml annotated batch buffer decode Jan Maslak @ 2026-04-08 9:23 ` Jani Nikula [not found] ` <20260407132620.1397340-2-jan.maslak@intel.com> ` (3 subsequent siblings) 6 siblings, 0 replies; 9+ messages in thread From: Jani Nikula @ 2026-04-08 9:23 UTC (permalink / raw) To: Jan Maslak, igt-dev; +Cc: zbigniew.kempczynski, Jan Maslak On Tue, 07 Apr 2026, Jan Maslak <jan.maslak@intel.com> wrote: > This series brings Mesa's hardware XML command/state definitions and > gen_pack_header.py code generator into IGT, adds a new IGT-written > batch buffer decoder (gen_decode_header.py), and converts rendercopy_gen9 > to use the generated pack headers. The cover letter and the commit messages contain a lot of the "What?" but there not much in terms of the "Why?" here. I can make assumptions, but the rationale is something that should be spelled out in the commit messages. BR, Jani. > > Patch 1 imports the XML definitions and generators. gen_pack_header.py > is taken from Mesa with C90 compliance fixes and a new baseline > deduplication mechanism - when a platform's command layout matches any > older generation exactly, the item is omitted entirely. > gen_decode_header.py is a new IGT-only file that generates per-platform > decoders for instructions, structs, and registers. > > Patch 2 converts rendercopy_gen9.c to use the generated pack headers, > replacing hand-written struct assignments and intel_bb_out() calls with > igt_genxml_emit and igt_genxml_pack_state. > > Patch 3 adds an opt-in annotated batch dump to intel_bb_dump(): when > IGT_BB_ANNOTATE=1 is set a companion .annotated file is written alongside > the raw hex dump, decoding each command's field names and values. > > Tested on LNL and DG2 (xe_render_copy render-square, render-full; > xe_intel_bb render) and TGL (gem_render_copy_redux; api_intel_bb). > > Signed-off-by: Jan Maslak <jan.maslak@intel.com> > > Jan Maslak (3): > lib/genxml: Import genxml definitions and generators from Mesa > lib/rendercopy: Convert rendercopy_gen9 to use genxml pack headers > lib: Add genxml annotated batch buffer decode > > lib/genxml/gen110.xml | 3358 +++++++++++++++++++++++++ > lib/genxml/gen120.xml | 2432 ++++++++++++++++++ > lib/genxml/gen125.xml | 2628 +++++++++++++++++++ > lib/genxml/gen40.xml | 1012 ++++++++ > lib/genxml/gen45.xml | 507 ++++ > lib/genxml/gen50.xml | 648 +++++ > lib/genxml/gen60.xml | 2606 +++++++++++++++++++ > lib/genxml/gen70.xml | 3067 ++++++++++++++++++++++ > lib/genxml/gen75.xml | 2424 ++++++++++++++++++ > lib/genxml/gen80.xml | 2993 ++++++++++++++++++++++ > lib/genxml/gen90.xml | 4192 +++++++++++++++++++++++++++++++ > lib/genxml/gen_decode_header.py | 487 ++++ > lib/genxml/gen_pack_header.py | 799 ++++++ > lib/genxml/igt_genxml.h | 112 + > lib/genxml/igt_genxml_decode.h | 60 + > lib/genxml/igt_genxml_defs.h | 335 +++ > lib/genxml/intel_genxml.py | 553 ++++ > lib/genxml/util.py | 39 + > lib/genxml/xe2.xml | 1969 +++++++++++++++ > lib/genxml/xe3.xml | 816 ++++++ > lib/genxml/xe3p.xml | 4 + > lib/intel_batchbuffer.c | 32 +- > lib/meson.build | 65 +- > lib/rendercopy_gen9.c | 1117 ++++---- > 24 files changed, 31687 insertions(+), 568 deletions(-) > create mode 100644 lib/genxml/gen110.xml > create mode 100644 lib/genxml/gen120.xml > create mode 100644 lib/genxml/gen125.xml > create mode 100644 lib/genxml/gen40.xml > create mode 100644 lib/genxml/gen45.xml > create mode 100644 lib/genxml/gen50.xml > create mode 100644 lib/genxml/gen60.xml > create mode 100644 lib/genxml/gen70.xml > create mode 100644 lib/genxml/gen75.xml > create mode 100644 lib/genxml/gen80.xml > create mode 100644 lib/genxml/gen90.xml > create mode 100644 lib/genxml/gen_decode_header.py > create mode 100644 lib/genxml/gen_pack_header.py > create mode 100644 lib/genxml/igt_genxml.h > create mode 100644 lib/genxml/igt_genxml_decode.h > create mode 100644 lib/genxml/igt_genxml_defs.h > create mode 100644 lib/genxml/intel_genxml.py > create mode 100644 lib/genxml/util.py > create mode 100644 lib/genxml/xe2.xml > create mode 100644 lib/genxml/xe3.xml > create mode 100644 lib/genxml/xe3p.xml -- Jani Nikula, Intel ^ permalink raw reply [flat|nested] 9+ messages in thread
[parent not found: <20260407132620.1397340-2-jan.maslak@intel.com>]
* Re: [PATCH 1/3] lib/genxml: Import genxml definitions and generators from Mesa [not found] ` <20260407132620.1397340-2-jan.maslak@intel.com> @ 2026-04-08 15:44 ` Kamil Konieczny 0 siblings, 0 replies; 9+ messages in thread From: Kamil Konieczny @ 2026-04-08 15:44 UTC (permalink / raw) To: Jan Maslak; +Cc: igt-dev, zbigniew.kempczynski Hi Jan, On 2026-04-07 at 15:26:18 +0200, Jan Maslak wrote: > Import the hardware command/state XML definitions, gen_pack_header.py, and > intel_genxml.py from Mesa (MIT-licensed, Mesa commit 3a62dc0218d3). Add a > new gen_decode_header.py written for IGT. The generators produce per-platform > *_pack.h and *_decode.h headers at build time into the build directory - no > generated files are committed to the source tree. Meson custom_target rules > build headers for gen9 through xe3p covering the render, blitter, and compute > engines. > > gen_pack_header.py produces type-safe pack and emit functions for every > command, struct, and register in the XML. Callers fill a typed struct and > call the pack function; the generator handles all bit-field packing. > > gen_decode_header.py (new, IGT-only) produces decoders that identify a command > from its opcode and print each decoded field's name and value. Also decodes > structs and registers embedded within commands. > > IGT-specific changes to gen_pack_header.py over the upstream Mesa version: > > - C90 compliance: block-scope each dword's local variable declarations in the > generated pack functions. > - Baseline deduplication: when a platform's layout exactly matches any older > generation, the item is omitted entirely - no #define aliases are emitted. > A comment names the oldest generation that first defined that layout so > the definition can be found in one grep. Upstream Mesa has no > deduplication; this keeps the generated headers free of noise as the > number of platform variants grows. > > See individual file headers for per-file copyright notices. > > Signed-off-by: Jan Maslak <jan.maslak@intel.com> > --- > lib/genxml/gen110.xml | 3358 +++++++++++++++++++++++++ All this imho should be placed in lib/intel/genxml as this is Intel specific. Could you also split this into commits under 1MB each? For example, two commits for XMLs and third for python scripts? Also, as Jani noted, please describe 'Why?' part in one of commits, preferably python one so it will stay in git history. Regards, Kamil > lib/genxml/gen120.xml | 2432 ++++++++++++++++++ > lib/genxml/gen125.xml | 2628 +++++++++++++++++++ > lib/genxml/gen40.xml | 1012 ++++++++ > lib/genxml/gen45.xml | 507 ++++ > lib/genxml/gen50.xml | 648 +++++ > lib/genxml/gen60.xml | 2606 +++++++++++++++++++ > lib/genxml/gen70.xml | 3067 ++++++++++++++++++++++ > lib/genxml/gen75.xml | 2424 ++++++++++++++++++ > lib/genxml/gen80.xml | 2993 ++++++++++++++++++++++ > lib/genxml/gen90.xml | 4192 +++++++++++++++++++++++++++++++ > lib/genxml/gen_decode_header.py | 487 ++++ > lib/genxml/gen_pack_header.py | 799 ++++++ > lib/genxml/igt_genxml.h | 112 + > lib/genxml/igt_genxml_decode.h | 60 + > lib/genxml/igt_genxml_defs.h | 335 +++ > lib/genxml/intel_genxml.py | 553 ++++ > lib/genxml/util.py | 39 + > lib/genxml/xe2.xml | 1969 +++++++++++++++ > lib/genxml/xe3.xml | 816 ++++++ > lib/genxml/xe3p.xml | 4 + > lib/meson.build | 65 +- > 22 files changed, 31105 insertions(+), 1 deletion(-) > create mode 100644 lib/genxml/gen110.xml > create mode 100644 lib/genxml/gen120.xml > create mode 100644 lib/genxml/gen125.xml > create mode 100644 lib/genxml/gen40.xml > create mode 100644 lib/genxml/gen45.xml > create mode 100644 lib/genxml/gen50.xml > create mode 100644 lib/genxml/gen60.xml > create mode 100644 lib/genxml/gen70.xml > create mode 100644 lib/genxml/gen75.xml > create mode 100644 lib/genxml/gen80.xml > create mode 100644 lib/genxml/gen90.xml > create mode 100644 lib/genxml/gen_decode_header.py > create mode 100644 lib/genxml/gen_pack_header.py > create mode 100644 lib/genxml/igt_genxml.h > create mode 100644 lib/genxml/igt_genxml_decode.h > create mode 100644 lib/genxml/igt_genxml_defs.h > create mode 100644 lib/genxml/intel_genxml.py > create mode 100644 lib/genxml/util.py > create mode 100644 lib/genxml/xe2.xml > create mode 100644 lib/genxml/xe3.xml > create mode 100644 lib/genxml/xe3p.xml > [cut] ^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Xe.CI.BAT: failure for lib/genxml: Introduce Mesa genxml infrastructure to IGT 2026-04-07 13:26 [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT Jan Maslak ` (3 preceding siblings ...) [not found] ` <20260407132620.1397340-2-jan.maslak@intel.com> @ 2026-04-09 17:45 ` Patchwork 2026-04-09 18:03 ` ✗ i915.CI.BAT: " Patchwork 2026-04-09 19:02 ` ✗ Xe.CI.FULL: " Patchwork 6 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2026-04-09 17:45 UTC (permalink / raw) To: Jan Maslak; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 4940 bytes --] == Series Details == Series: lib/genxml: Introduce Mesa genxml infrastructure to IGT URL : https://patchwork.freedesktop.org/series/164446/ State : failure == Summary == CI Bug Log - changes from XEIGT_8852_BAT -> XEIGTPW_14944_BAT ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with XEIGTPW_14944_BAT absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in XEIGTPW_14944_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (14 -> 14) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in XEIGTPW_14944_BAT: ### IGT changes ### #### Possible regressions #### * igt@xe_pat@pat-index-xe2: - bat-bmg-1: [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-bmg-1/igt@xe_pat@pat-index-xe2.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-bmg-1/igt@xe_pat@pat-index-xe2.html - bat-lnl-2: [PASS][3] -> [INCOMPLETE][4] +1 other test incomplete [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-lnl-2/igt@xe_pat@pat-index-xe2.html [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-lnl-2/igt@xe_pat@pat-index-xe2.html - bat-wcl-1: [PASS][5] -> [INCOMPLETE][6] +1 other test incomplete [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-wcl-1/igt@xe_pat@pat-index-xe2.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-wcl-1/igt@xe_pat@pat-index-xe2.html - bat-wcl-2: [PASS][7] -> [INCOMPLETE][8] +1 other test incomplete [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-wcl-2/igt@xe_pat@pat-index-xe2.html [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-wcl-2/igt@xe_pat@pat-index-xe2.html - bat-ptl-2: [PASS][9] -> [INCOMPLETE][10] +1 other test incomplete [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-ptl-2/igt@xe_pat@pat-index-xe2.html [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-ptl-2/igt@xe_pat@pat-index-xe2.html * igt@xe_pat@pat-index-xe2@render: - bat-ptl-1: [PASS][11] -> [INCOMPLETE][12] +1 other test incomplete [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-ptl-1/igt@xe_pat@pat-index-xe2@render.html [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-ptl-1/igt@xe_pat@pat-index-xe2@render.html - bat-ptl-vm: [PASS][13] -> [INCOMPLETE][14] +1 other test incomplete [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-ptl-vm/igt@xe_pat@pat-index-xe2@render.html [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-ptl-vm/igt@xe_pat@pat-index-xe2@render.html - bat-lnl-1: [PASS][15] -> [INCOMPLETE][16] +1 other test incomplete [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-lnl-1/igt@xe_pat@pat-index-xe2@render.html [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-lnl-1/igt@xe_pat@pat-index-xe2@render.html - bat-bmg-2: [PASS][17] -> [INCOMPLETE][18] +1 other test incomplete [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-bmg-2/igt@xe_pat@pat-index-xe2@render.html [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-bmg-2/igt@xe_pat@pat-index-xe2@render.html Known issues ------------ Here are the changes found in XEIGTPW_14944_BAT that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1: - bat-adlp-7: [PASS][19] -> [DMESG-WARN][20] ([Intel XE#7483]) [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html #### Possible fixes #### * igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1: - bat-adlp-7: [DMESG-WARN][21] ([Intel XE#7483]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html [Intel XE#7483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7483 Build changes ------------- * IGT: IGT_8852 -> IGTPW_14944 IGTPW_14944: 14944 IGT_8852: 8852 xe-4860-5ee75b2816df74bfe606d4dfc061547d5cda4ebf: 5ee75b2816df74bfe606d4dfc061547d5cda4ebf == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/index.html [-- Attachment #2: Type: text/html, Size: 5712 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ i915.CI.BAT: failure for lib/genxml: Introduce Mesa genxml infrastructure to IGT 2026-04-07 13:26 [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT Jan Maslak ` (4 preceding siblings ...) 2026-04-09 17:45 ` ✗ Xe.CI.BAT: failure for lib/genxml: Introduce Mesa genxml infrastructure to IGT Patchwork @ 2026-04-09 18:03 ` Patchwork 2026-04-09 19:02 ` ✗ Xe.CI.FULL: " Patchwork 6 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2026-04-09 18:03 UTC (permalink / raw) To: Jan Maslak; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 3214 bytes --] == Series Details == Series: lib/genxml: Introduce Mesa genxml infrastructure to IGT URL : https://patchwork.freedesktop.org/series/164446/ State : failure == Summary == CI Bug Log - changes from IGT_8852 -> IGTPW_14944 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_14944 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_14944, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14944/index.html Participating hosts (42 -> 40) ------------------------------ Missing (2): bat-dg2-13 fi-snb-2520m Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_14944: ### IGT changes ### #### Possible regressions #### * igt@gem_exec_fence@basic-await: - bat-arls-5: [PASS][1] -> [FAIL][2] +1 other test fail [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8852/bat-arls-5/igt@gem_exec_fence@basic-await.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14944/bat-arls-5/igt@gem_exec_fence@basic-await.html Known issues ------------ Here are the changes found in IGTPW_14944 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@i915_selftest@live@workarounds: - bat-arls-5: [DMESG-FAIL][3] ([i915#12061]) -> [PASS][4] +1 other test pass [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8852/bat-arls-5/igt@i915_selftest@live@workarounds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14944/bat-arls-5/igt@i915_selftest@live@workarounds.html - bat-dg2-9: [DMESG-FAIL][5] ([i915#12061]) -> [PASS][6] +1 other test pass [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8852/bat-dg2-9/igt@i915_selftest@live@workarounds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14944/bat-dg2-9/igt@i915_selftest@live@workarounds.html - bat-dg2-14: [DMESG-FAIL][7] ([i915#12061]) -> [PASS][8] +1 other test pass [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8852/bat-dg2-14/igt@i915_selftest@live@workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14944/bat-dg2-14/igt@i915_selftest@live@workarounds.html - bat-mtlp-9: [DMESG-FAIL][9] ([i915#12061]) -> [PASS][10] +1 other test pass [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8852/bat-mtlp-9/igt@i915_selftest@live@workarounds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14944/bat-mtlp-9/igt@i915_selftest@live@workarounds.html [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_8852 -> IGTPW_14944 CI-20190529: 20190529 CI_DRM_18303: 7fa61e7003dda66c77b7f63a555658d8fb10bacf @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_14944: 14944 IGT_8852: 8852 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14944/index.html [-- Attachment #2: Type: text/html, Size: 4085 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Xe.CI.FULL: failure for lib/genxml: Introduce Mesa genxml infrastructure to IGT 2026-04-07 13:26 [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT Jan Maslak ` (5 preceding siblings ...) 2026-04-09 18:03 ` ✗ i915.CI.BAT: " Patchwork @ 2026-04-09 19:02 ` Patchwork 6 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2026-04-09 19:02 UTC (permalink / raw) To: Jan Maslak; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 19749 bytes --] == Series Details == Series: lib/genxml: Introduce Mesa genxml infrastructure to IGT URL : https://patchwork.freedesktop.org/series/164446/ State : failure == Summary == CI Bug Log - changes from XEIGT_8852_FULL -> XEIGTPW_14944_FULL ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with XEIGTPW_14944_FULL absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in XEIGTPW_14944_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (2 -> 2) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in XEIGTPW_14944_FULL: ### IGT changes ### #### Possible regressions #### * igt@xe_pat@display-vs-wb-transient: - shard-bmg: [PASS][1] -> [INCOMPLETE][2] +2 other tests incomplete [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-5/igt@xe_pat@display-vs-wb-transient.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-4/igt@xe_pat@display-vs-wb-transient.html - shard-lnl: [PASS][3] -> [INCOMPLETE][4] +2 other tests incomplete [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-lnl-2/igt@xe_pat@display-vs-wb-transient.html [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-lnl-2/igt@xe_pat@display-vs-wb-transient.html Known issues ------------ Here are the changes found in XEIGTPW_14944_FULL that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2: - shard-bmg: [PASS][5] -> [INCOMPLETE][6] ([Intel XE#6819] / [Intel XE#6891]) [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-10/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html * igt@kms_atomic_transition@plane-all-transition-nonblocking: - shard-bmg: [PASS][7] -> [INCOMPLETE][8] ([Intel XE#6819]) +1 other test incomplete [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-1/igt@kms_atomic_transition@plane-all-transition-nonblocking.html [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-3/igt@kms_atomic_transition@plane-all-transition-nonblocking.html * igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-a-hdmi-a-3: - shard-bmg: [PASS][9] -> [DMESG-WARN][10] ([Intel XE#6819]) [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-1/igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-a-hdmi-a-3.html [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-3/igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-a-hdmi-a-3.html * igt@kms_big_fb@y-tiled-8bpp-rotate-90: - shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#1124]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-10/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-addfb: - shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#2328] / [Intel XE#7367]) [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-10/igt@kms_big_fb@yf-tiled-addfb.html * igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p: - shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#7679]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-7/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs: - shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2887]) +5 other tests skip [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-7/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html * igt@kms_chamelium_hpd@dp-hpd-fast: - shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2252]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-10/igt@kms_chamelium_hpd@dp-hpd-fast.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-bmg: [PASS][16] -> [FAIL][17] ([Intel XE#7571]) [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-9/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html * igt@kms_dp_link_training@uhbr-mst: - shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#4354] / [Intel XE#7386]) [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-5/igt@kms_dp_link_training@uhbr-mst.html * igt@kms_flip@plain-flip-fb-recreate@d-dp2: - shard-bmg: [PASS][19] -> [ABORT][20] ([Intel XE#5545] / [Intel XE#6652] / [Intel XE#7200]) +1 other test abort [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-9/igt@kms_flip@plain-flip-fb-recreate@d-dp2.html [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-2/igt@kms_flip@plain-flip-fb-recreate@d-dp2.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling: - shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#7178] / [Intel XE#7351]) [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-10/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt: - shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#4141]) +2 other tests skip [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-blt: - shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2311]) +8 other tests skip [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt: - shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#2313]) +6 other tests skip [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html * igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-b-plane-5: - shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#7130]) +1 other test skip [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-1/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-b-plane-5.html * igt@kms_pm_backlight@fade-with-suspend: - shard-lnl: [PASS][26] -> [ABORT][27] ([Intel XE#2625]) +1 other test abort [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-lnl-1/igt@kms_pm_backlight@fade-with-suspend.html [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-lnl-6/igt@kms_pm_backlight@fade-with-suspend.html * igt@kms_pm_dc@dc6-dpms: - shard-lnl: [PASS][28] -> [FAIL][29] ([Intel XE#7340]) [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-lnl-5/igt@kms_pm_dc@dc6-dpms.html [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-lnl-2/igt@kms_pm_dc@dc6-dpms.html * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf: - shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#1489]) [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-4/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html * igt@kms_psr@fbc-pr-primary-page-flip: - shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#2234] / [Intel XE#2850]) +4 other tests skip [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-8/igt@kms_psr@fbc-pr-primary-page-flip.html * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0: - shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#3904] / [Intel XE#7342]) [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-10/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html * igt@kms_vrr@cmrr@pipe-a-edp-1: - shard-lnl: [PASS][33] -> [FAIL][34] ([Intel XE#4459]) +1 other test fail [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-lnl-4/igt@kms_vrr@cmrr@pipe-a-edp-1.html [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-lnl-6/igt@kms_vrr@cmrr@pipe-a-edp-1.html * igt@kms_vrr@lobf: - shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2168] / [Intel XE#7444]) [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-1/igt@kms_vrr@lobf.html * igt@xe_eudebug@basic-exec-queues: - shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#7636]) +4 other tests skip [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-5/igt@xe_eudebug@basic-exec-queues.html * igt@xe_evict@evict-mixed-many-threads-small: - shard-bmg: NOTRUN -> [INCOMPLETE][37] ([Intel XE#6321]) [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html * igt@xe_evict@evict-small-multi-queue-priority-cm: - shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#7140]) [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-9/igt@xe_evict@evict-small-multi-queue-priority-cm.html * igt@xe_exec_basic@multigpu-no-exec-null: - shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#2322] / [Intel XE#7372]) [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-4/igt@xe_exec_basic@multigpu-no-exec-null.html * igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind: - shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#7136]) +6 other tests skip [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-1/igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind.html * igt@xe_exec_multi_queue@many-execs-preempt-mode-priority: - shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#6874]) +10 other tests skip [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-9/igt@xe_exec_multi_queue@many-execs-preempt-mode-priority.html * igt@xe_exec_threads@threads-multi-queue-cm-fd-rebind: - shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#7138]) +3 other tests skip [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-10/igt@xe_exec_threads@threads-multi-queue-cm-fd-rebind.html * igt@xe_pxp@pxp-termination-key-update-post-suspend: - shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#4733] / [Intel XE#7417]) [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-4/igt@xe_pxp@pxp-termination-key-update-post-suspend.html * igt@xe_query@multigpu-query-pxp-status: - shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#944]) [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-6/igt@xe_query@multigpu-query-pxp-status.html * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs: - shard-bmg: [PASS][45] -> [FAIL][46] ([Intel XE#5937]) +1 other test fail [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-6/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-6/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html #### Possible fixes #### * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: - shard-bmg: [DMESG-WARN][47] ([Intel XE#5354]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-5/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-8/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html * igt@kms_flip@2x-wf_vblank-ts-check-interruptible: - shard-bmg: [FAIL][49] ([Intel XE#3149]) -> [PASS][50] +1 other test pass [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-4/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html * igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ad-dp2-hdmi-a3: - shard-bmg: [FAIL][51] -> [PASS][52] +4 other tests pass [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ad-dp2-hdmi-a3.html [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-4/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ad-dp2-hdmi-a3.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-lnl: [FAIL][53] ([Intel XE#301]) -> [PASS][54] +1 other test pass [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html * igt@kms_vrr@flip-basic: - shard-lnl: [FAIL][55] ([Intel XE#4227] / [Intel XE#7397]) -> [PASS][56] +3 other tests pass [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-lnl-8/igt@kms_vrr@flip-basic.html [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-lnl-2/igt@kms_vrr@flip-basic.html * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1: - shard-lnl: [FAIL][57] ([Intel XE#2142]) -> [PASS][58] +1 other test pass [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-lnl-6/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-lnl-6/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html * igt@xe_exec_system_allocator@many-execqueues-mmap-shared-remap-eocheck: - shard-bmg: [DMESG-WARN][59] -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-6/igt@xe_exec_system_allocator@many-execqueues-mmap-shared-remap-eocheck.html [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-4/igt@xe_exec_system_allocator@many-execqueues-mmap-shared-remap-eocheck.html * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs: - shard-bmg: [FAIL][61] ([Intel XE#5937]) -> [PASS][62] +2 other tests pass [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-8/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs.html [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-8/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs.html #### Warnings #### * igt@kms_tiled_display@basic-test-pattern-with-chamelium: - shard-bmg: [SKIP][63] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][64] ([Intel XE#2426] / [Intel XE#5848]) [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8852/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124 [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489 [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142 [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168 [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234 [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252 [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311 [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313 [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322 [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328 [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426 [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509 [Intel XE#2625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2625 [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850 [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887 [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301 [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149 [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904 [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141 [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227 [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354 [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459 [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733 [Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354 [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545 [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848 [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937 [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321 [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652 [Intel XE#6819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6819 [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874 [Intel XE#6891]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6891 [Intel XE#7130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7130 [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136 [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138 [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140 [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178 [Intel XE#7200]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7200 [Intel XE#7340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7340 [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342 [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351 [Intel XE#7367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7367 [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372 [Intel XE#7386]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7386 [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397 [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417 [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437 [Intel XE#7444]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7444 [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571 [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636 [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679 [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944 Build changes ------------- * IGT: IGT_8852 -> IGTPW_14944 IGTPW_14944: 14944 IGT_8852: 8852 xe-4860-5ee75b2816df74bfe606d4dfc061547d5cda4ebf: 5ee75b2816df74bfe606d4dfc061547d5cda4ebf == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14944/index.html [-- Attachment #2: Type: text/html, Size: 21402 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
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2026-04-07 13:26 [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT Jan Maslak
2026-04-07 13:26 ` [PATCH 2/3] lib/rendercopy: Convert rendercopy_gen9 to use genxml pack headers Jan Maslak
2026-04-07 15:00 ` Ville Syrjälä
2026-04-07 13:26 ` [PATCH 3/3] lib: Add genxml annotated batch buffer decode Jan Maslak
2026-04-08 9:23 ` [PATCH 0/3] lib/genxml: Introduce Mesa genxml infrastructure to IGT Jani Nikula
[not found] ` <20260407132620.1397340-2-jan.maslak@intel.com>
2026-04-08 15:44 ` [PATCH 1/3] lib/genxml: Import genxml definitions and generators from Mesa Kamil Konieczny
2026-04-09 17:45 ` ✗ Xe.CI.BAT: failure for lib/genxml: Introduce Mesa genxml infrastructure to IGT Patchwork
2026-04-09 18:03 ` ✗ i915.CI.BAT: " Patchwork
2026-04-09 19:02 ` ✗ Xe.CI.FULL: " Patchwork
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