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X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7bJ2HYdjZPZUFok+or/pIpUM3fThuAYeR8GVy07EWEHqbzfp/djjxqxytnkvQmwbWkVNzfz5C93soTwP2aHDbkmiy504qr7znkJJ5rjhV/U= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR11MB5280 X-OriginatorOrg: intel.com X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On Tue, Oct 13, 2026 at 10:12:15AM +0530, Shekhar Chauhan wrote: >Extend tail-address-wrap to all OA units and force the 192B format on >Xe3+ OAM to properly test it since other formats on OAM don't use 192B >on Xe3+ platforms. > >Signed-off-by: Shekhar Chauhan >--- > tests/intel/xe_oa.c | 31 +++++++++++++++++++++++++++++-- > 1 file changed, 29 insertions(+), 2 deletions(-) > >diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c >index 9ebb18690..d6c3c4a6d 100644 >--- a/tests/intel/xe_oa.c >+++ b/tests/intel/xe_oa.c >@@ -4516,6 +4516,29 @@ static void closed_fd_and_unmapped_access(const struct drm_xe_oa_unit *oau) > try_invalid_access(vaddr); > } > >+static bool oam_has_tail_address_wrap(const struct drm_xe_oa_unit *oau) >+{ >+ const struct drm_xe_gt *gt; >+ >+ if ((oau->oa_unit_type != DRM_XE_OA_UNIT_TYPE_OAM && >+ oau->oa_unit_type != DRM_XE_OA_UNIT_TYPE_OAM_SAG) || >+ !(oau->capabilities & DRM_XE_OA_CAPS_OA_UNIT_GT_ID)) >+ return false; >+ >+ gt = drm_xe_get_gt(xe_device_get(drm_fd), oau->gt_id); >+ >+ return gt && gt->ip_ver_major >= 30; >+} >+ >+static int tail_address_wrap_format(const struct drm_xe_oa_unit *oau) >+{ >+ /* Default OAM metric sets use a power-of-2 report size */ I think the comment should instead be /* Pick a non-power-of-2 OAM format to verify tail address wrap */ >+ if (oam_has_tail_address_wrap(oau)) >+ return XE_OAM_FORMAT_MPEC8u64_B8_C8; >+ >+ return oa_unit_metric_set(oau)->perf_oa_format; >+} >+ > /** > * SUBTEST: tail-address-wrap > * Description: Test tail address wrap on odd format sizes. Ensure that the >@@ -4530,7 +4553,7 @@ test_tail_address_wrap(const struct drm_xe_oa_unit *oau, size_t oa_buffer_size) > struct intel_xe_perf_metric_set *test_set = oa_unit_metric_set(oau); > u64 exponent = max_oa_exponent_for_period_lte(20000); > u64 buffer_size = oa_buffer_size ?: buffer_fill_size; >- u64 fmt = test_set->perf_oa_format; >+ u64 fmt = tail_address_wrap_format(oau); > u64 properties[] = { > DRM_XE_OA_PROPERTY_OA_UNIT_ID, oau->oa_unit_id, > DRM_XE_OA_PROPERTY_SAMPLE_OA, true, >@@ -4879,6 +4902,10 @@ exit: > for_each_oa_unit(oau) \ > igt_dynamic_f("%s-%d", oa_unit_name[oau->oa_unit_type], oau->oa_unit_id) > >+#define __for_each_oa_unit_with_arg(oau, str) \ >+ for_each_oa_unit(oau) \ >+ igt_dynamic_f("%s-%d-%s", oa_unit_name[oau->oa_unit_type], oau->oa_unit_id, str) >+ Maybe I did not think this through when you asked me offline. I think we should still prevent the tail_address_wrap from running on platforms with OAMs that do not supports it. See LNL failure in CI. With this patch it runs the test on LNL OAM and then skips it because it chooses a power of 2 OAM format (so area_size is 0). Otherwise we have the SKIP noise in CI that will need occasional addressing. Now it flags it as NOTRUN -> SKIP. Thoughts? i.e. __for_each_oa_unit_with_tail_address_wrap() ... Thanks, Umesh > static int opt_handler(int opt, int opt_index, void *data) > { > uint32_t tmp; >@@ -5146,7 +5173,7 @@ int igt_main_args("b:td", long_options, help_str, opt_handler, NULL) > long k = random() % num_buf_sizes; > > igt_require(oau0->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE); >- __for_oa_unit_by_type_w_arg(DRM_XE_OA_UNIT_TYPE_OAG, buf_sizes[k].name) >+ __for_each_oa_unit_with_arg(oau, buf_sizes[k].name) > test_tail_address_wrap(oau, buf_sizes[k].size); > } > >-- >2.53.0 _