Re: tests/intel/xe_pm_residency: skip cpg-gt-toggle if GT not in C6

["Poosa, Karthik" <karthik.poosa@intel.com>]

On 05-05-2026 01:58, Sk Anirban wrote:
> The test assumes GTs are idle before forcewake is acquired and power-gate
> status is validated. If a prior subtest leaves a GT in C0 (GT stays active
> for any reason), the final power-gate checks can fail for the wrong reason.
> Add an skip so that inability to enter C6 is treated as a missing
> prerequisite.
>
> Signed-off-by: Sk Anirban <sk.anirban@intel.com>
> ---
>   tests/intel/xe_pm_residency.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
> index 1eeabd509..bfae1f844 100644
> --- a/tests/intel/xe_pm_residency.c
> +++ b/tests/intel/xe_pm_residency.c
> @@ -392,8 +392,8 @@ static void cpg_gt_toggle(int fd)
>   	int gt;
>   
>   	xe_for_each_gt(fd, gt)
> -		igt_assert_f(igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 10),
> -			     "GT %d should be in C6\n", gt);
> +		igt_skip_on_f(!igt_wait(xe_gt_is_in_c6(fd, gt), 1000, 10),
> +			      "GT %d is not in C6\n", gt);
>   
>   	fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY);
>   	igt_assert_lte(0, fw_handle);

LGTM.

Reviewed-by: Karthik Poosa <karthik.poosa@intel.com>

Follow up this patch with 
https://patchwork.freedesktop.org/series/163104/  adding power powergate 
when not in C6.