Re: [PATCH i-g-t] tests/intel/kms_pm_dc: Remove deep-pkgc subtest

["Sharma, Swati2" <swati2.sharma@intel.com>]

Hi Thasleem,

Please send the revert of

commit 4d9b4ee12b5f0852c02818ca9a886355b43fbbff
Author: Jeevan B <jeevan.b@intel.com>
Date:   Thu May 30 12:45:40 2024 +0530

     tests/intel/kms_pm_dc: Add a new test to validate the deep sleep 
state during extended vblank

++Kamil

On 16-04-2026 05:01 pm, Mohammed Thasleem wrote:
> Remove the deep-pkgc subtest as it depends on other display IPs which makes
> testing unreliable. Current validation uses Package C-state counters that
> are affected by unrelated system components and requires platform-specific
> checks that vary across different platforms.
> A redesigned test with proper display IP isolation will be implemented
> in a future patch.
>
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>   tests/intel/kms_pm_dc.c | 96 -----------------------------------------
>   1 file changed, 96 deletions(-)
>
> diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
> index 8138933d4..44394305d 100644
> --- a/tests/intel/kms_pm_dc.c
> +++ b/tests/intel/kms_pm_dc.c
> @@ -72,9 +72,6 @@
>    * SUBTEST: dc9-dpms
>    * Description: This test validates display engine entry to DC9 state
>    *
> - * SUBTEST: deep-pkgc
> - * Description: This test validates display engine entry to PKGC10 state for extended vblank
> - *
>    * SUBTEST: dc5-retention-flops
>    * Description: This test validates display engine entry to DC5 state while PSR is active on Pipe B
>    */
> @@ -535,90 +532,6 @@ static int has_panels_without_dc_support(igt_display_t *display)
>   	return external_panel;
>   }
>   
> -static void test_deep_pkgc_state(data_t *data)
> -{
> -	unsigned int pre_val = 0, cur_val = 0;
> -	time_t start = time(NULL);
> -	time_t duration = (4 * SEC);
> -	time_t delay;
> -	igt_crtc_t *crtc;
> -	bool pkgc_flag = false;
> -	bool flip = true, edp_found = false;
> -
> -	igt_display_t *display = &data->display;
> -	igt_plane_t *primary;
> -	igt_output_t *output = NULL;
> -	drmModeModeInfo *mode;
> -
> -	for_each_crtc_with_valid_output(display, crtc, output) {
> -		if (output->config.connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> -
> -			edp_found = true;
> -			/* Check VRR capabilities before setting up */
> -			if (igt_output_has_prop(output, IGT_CONNECTOR_VRR_CAPABLE) &&
> -			    igt_output_get_prop(output, IGT_CONNECTOR_VRR_CAPABLE)) {
> -				/*
> -				 * TODO: Add check for vmin = vmax = flipline if VRR enabled
> -				 * when KMD allows for such capability.
> -				 */
> -				igt_crtc_set_prop_value(crtc, IGT_CRTC_VRR_ENABLED, false);
> -				igt_assert(igt_display_try_commit_atomic(display,
> -									 DRM_MODE_ATOMIC_ALLOW_MODESET,
> -									 NULL) == 0);
> -			}
> -			break;
> -		}
> -	}
> -
> -	if (!edp_found) {
> -		igt_skip("No eDP output found, skipping the test.\n");
> -		return;
> -	}
> -
> -	igt_display_reset(display);
> -
> -	igt_output_set_crtc(output, crtc);
> -	for_each_connector_mode(output, mode) {
> -		data->mode = mode;
> -		delay = (MSEC / (data->mode->vrefresh));
> -		/*
> -		 * Should be 5ms vblank time required to program higher
> -		 * watermark levels
> -		 */
> -		if (delay >= (5 * MSEC))
> -			break;
> -	}
> -
> -	data->output = output;
> -	setup_videoplayback(data);
> -
> -	primary = igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY);
> -	igt_plane_set_fb(primary, &data->fb_rgb);
> -	igt_display_commit(&data->display);
> -	/* Wait for the vblank to sync the frame time */
> -	igt_wait_for_vblank_count(crtc, 1);
> -	pre_val = igt_read_pkgc_counter(data->debugfs_root_fd);
> -	/* Add a half-frame delay to ensure the flip occurs when the frame is active. */
> -	usleep(delay * 0.5);
> -
> -	while (time(NULL) - start < duration) {
> -		flip = !flip;
> -		igt_plane_set_fb(primary, flip ? &data->fb_rgb : &data->fb_rgr);
> -		igt_display_commit(&data->display);
> -
> -		igt_wait((cur_val = igt_read_pkgc_counter(data->debugfs_root_fd)) > pre_val,
> -			 (delay * 2), (5 * MSEC));
> -
> -		if (cur_val > pre_val) {
> -			pkgc_flag = true;
> -			break;
> -		}
> -	}
> -
> -	cleanup_dc3co_fbs(data);
> -	igt_assert_f(pkgc_flag, "PKGC10 is not achieved.\n");
> -}
> -
>   static void kms_poll_state_restore(int sig)
>   {
>   	int sysfs_fd;
> @@ -685,15 +598,6 @@ int igt_main()
>   		test_dc_state_psr(&data, IGT_INTEL_CHECK_DC6);
>   	}
>   
> -	igt_describe("This test validates display engine entry to PKGC10 state "
> -		     "during extended vblank");
> -	igt_subtest("deep-pkgc") {
> -		igt_require_f(igt_pm_pc8_plus_residencies_enabled(data.msr_fd),
> -			      "PC8+ residencies not supported\n");
> -		igt_require(intel_display_ver(data.devid) >= 20);
> -		test_deep_pkgc_state(&data);
> -	}
> -
>   	igt_describe("This test validates display engine entry to DC5 state "
>   		     "while all connectors's DPMS property set to OFF");
>   	igt_subtest("dc5-dpms") {