[igt-dev] [PATCH 03/10] gem_ctx_isolation.c/tgl - Gen12 enabling for context isolation test

Lucas De Marchi
2019-07-15T21:51:45Z

From: Dale B Stimson <dale.b.stimson@intel.com>

For Gen12:

Enable test execution.

Tests have been disabled for registers which Gen12 made privileged
and which are not in the kernel whitelist.

Tests have been added for context register(s) added to the kernel
whitelist for Gen12.

Previously present registers that are no longer in the render context
have been removed.

Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
tests/i915/gem_ctx_isolation.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index c4302394..cd0c836e 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -55,10 +55,11 @@ enum {
#define GEN9 (ALL << 9)
#define GEN10 (ALL << 10)
#define GEN11 (ALL << 11)
+#define GEN12 (ALL << 12)

#define NOCTX 0

-#define LAST_KNOWN_GEN 11
+#define LAST_KNOWN_GEN 12

static const struct named_register {
const char *name;
@@ -116,9 +117,12 @@ static const struct named_register {
{ "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
{ "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
{ "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
- { "L3_Config", GEN8, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff },
- { "TD_CTL2", GEN8, RCS0, 0xe404 },
+
+ /* Gen12: these registers became privileged, are not in whitelist. */
+ { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
+ { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff },
+ { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
+
{ "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
{ "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
{ "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
@@ -145,6 +149,8 @@ static const struct named_register {
{ "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
{ "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
{ "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true },
+ { "COMMON_SLICE_CHICKEN2", GEN_RANGE(12, 12), RCS0, 0x7014, .masked = true },
+ /* SAMPLER_MODE - Gen12 - In whitelist, but no longer in context. */
{ "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },

{ "BCS_GPR", GEN9, BCS0, 0x22600, 32 },