Re: [PATCH i-g-t] lib/intel_bufops: Set NEEDS_VISIBLE_VRAM for each buf by default

[Matthew Auld <matthew.auld@intel.com>]

On 05/12/2024 10:41, Dominik Grzegorzek wrote:
> Some tests (i.e. xe_eudebug_online, xe_exec_sip) are mapping intel_buf.
> If the backing storage is nvram, any access to mmaped buffer may
> cause segmentation fault. Set DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM
> by default as intel_bufs might be mapped and this is not harmful.

There is the downside that all objects will now be limited to BAR size 
when using this API. i.e you might have 16G VRAM but only 256M BAR. But 
I guess user can always pass in their own handle if they need something 
more special, so NEEDS_VISIBLE_VRAM is probably a sensible default and 
most tests probably don't care about the limit? Ideally the API would 
have an option to hint that CPU access is something they actually need.

Also: https://patchwork.freedesktop.org/series/141710/

> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> ---
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> 
>   lib/intel_bufops.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
> index 619222019..49b91a171 100644
> --- a/lib/intel_bufops.c
> +++ b/lib/intel_bufops.c
> @@ -1021,7 +1021,8 @@ static void __intel_buf_init(struct buf_ops *bops,
>   				cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
>   
>   			bo_size = ALIGN(bo_size, xe_get_default_alignment(bops->fd));
> -			buf->handle = xe_bo_create_caching(bops->fd, 0, bo_size, region, 0,
> +			buf->handle = xe_bo_create_caching(bops->fd, 0, bo_size, region,
> +							   DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
>   							   cpu_caching);
>   		}
>   	}