From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2041.outbound.protection.outlook.com [40.107.101.41]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A8F410E21D for ; Tue, 8 Aug 2023 20:34:29 +0000 (UTC) Message-ID: Date: Tue, 8 Aug 2023 14:34:25 -0600 Content-Language: en-US To: Aurabindo Pillai , igt-dev@lists.freedesktop.org References: <20230808152419.1454608-1-aurabindo.pillai@amd.com> <20230808152419.1454608-2-aurabindo.pillai@amd.com> From: Alex Hung In-Reply-To: <20230808152419.1454608-2-aurabindo.pillai@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH v3 2/2] tests/amdgpu: Add test for MALL static screen cache scanout List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Reviewed-by: Alex Hung On 2023-08-08 09:24, Aurabindo Pillai wrote: > MALL stands for memory access at last level. > > This test is to verify that the display scanout is triggered from MALL cache instead > of GPU VRAM when the contents of the screen is idle for some time. > > Requires UMR userspace utility from > https://gitlab.freedesktop.org/tomstdenis/umr to read MALL register > value. > > This test commits a test pattern FB, sleeps for some > time, and then reads back the MALL status register to check if display > refresh from static screen is triggered. > > Changes in v2: > > Added possibility to skip the test on Asics that do not support MALL > > Changes in v3: > > Aded comment in source code about the MALL delay time necessary to > trigger idle optimizations. > > Signed-off-by: Aurabindo Pillai > --- > tests/amdgpu/amd_mall.c | 169 +++++++++++++++++++++++++++++++++++++++ > tests/amdgpu/meson.build | 1 + > 2 files changed, 170 insertions(+) > create mode 100644 tests/amdgpu/amd_mall.c > > diff --git a/tests/amdgpu/amd_mall.c b/tests/amdgpu/amd_mall.c > new file mode 100644 > index 000000000..c50d046ee > --- /dev/null > +++ b/tests/amdgpu/amd_mall.c > @@ -0,0 +1,169 @@ > +/* > + * Copyright 2023 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include "igt.h" > +#include "igt_amd.h" > +#include "igt_core.h" > +#include > + > +IGT_TEST_DESCRIPTION("Test display refresh from MALL cache"); > + > +/* > + * Time needed in seconds for vblank irq count to reach 0. > + * Typically about 5 seconds. > + */ > + > +#define MALL_SETTLE_DELAY 10 > + > +/* Common test data. */ > +typedef struct data { > + igt_display_t display; > + igt_plane_t *primary; > + igt_output_t *output; > + igt_pipe_t *pipe; > + igt_pipe_crc_t *pipe_crc; > + drmModeModeInfo *mode; > + enum pipe pipe_id; > + int fd; > + int w; > + int h; > +} data_t; > + > +struct line_check { > + int found; > + const char *substr; > +}; > + > +/* Common test setup. */ > +static void test_init(data_t *data) > +{ > + igt_display_t *display = &data->display; > + bool mall_capable = false; > + > + /* It doesn't matter which pipe we choose on amdpgu. */ > + data->pipe_id = PIPE_A; > + data->pipe = &data->display.pipes[data->pipe_id]; > + > + igt_display_reset(display); > + > + mall_capable = igt_amd_is_mall_capable(data->fd); > + igt_require_f(mall_capable, "Requires hardware that supports MALL cache\n"); > + > + /* find a connected output */ > + data->output = NULL; > + for (int i=0; i < data->display.n_outputs; ++i) { > + drmModeConnector *connector = data->display.outputs[i].config.connector; > + if (connector->connection == DRM_MODE_CONNECTED) { > + data->output = &data->display.outputs[i]; > + } > + } > + igt_require_f(data->output, "Requires a connected display\n"); > + > + data->mode = igt_output_get_mode(data->output); > + igt_assert(data->mode); > + > + data->primary = > + igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY); > + > + data->pipe_crc = igt_pipe_crc_new(data->fd, data->pipe_id, > + IGT_PIPE_CRC_SOURCE_AUTO); > + > + igt_output_set_pipe(data->output, data->pipe_id); > + > + data->w = data->mode->hdisplay; > + data->h = data->mode->vdisplay; > +} > + > +/* Common test cleanup. */ > +static void test_fini(data_t *data) > +{ > + igt_pipe_crc_free(data->pipe_crc); > + igt_display_reset(&data->display); > + igt_display_commit_atomic(&data->display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0); > +} > + > +static bool check_cmd_output(const char *line, void *data) > +{ > + struct line_check *check = data; > + > + if (strstr(line, check->substr)) { > + check->found++; > + } > + > + return false; > +} > +static void test_mall_ss(data_t *data) > +{ > + igt_display_t *display = &data->display; > + igt_fb_t rfb; > + int exec_ret; > + struct line_check line = {0}; > + > + test_init(data); > + > + igt_create_pattern_fb(data->fd, data->w, data->h, DRM_FORMAT_XRGB8888, 0, &rfb); > + igt_plane_set_fb(data->primary, &rfb); > + igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL); > + > + sleep(MALL_SETTLE_DELAY); > + > + igt_system_cmd(exec_ret, "umr -O bits -r *.*.HUBP0_HUBP_MALL_STATUS | grep MALL_IN_USE"); > + > + igt_skip_on_f(exec_ret != IGT_EXIT_SUCCESS, "Error running UMR\n"); > + > + line.substr = "1 (0x00000001)"; > + igt_log_buffer_inspect(check_cmd_output, &line); > + > + igt_assert_eq(line.found, 1); > + > + igt_remove_fb(data->fd, &rfb); > + test_fini(data); > +} > + > +igt_main > +{ > + data_t data; > + > + igt_skip_on_simulation(); > + > + memset(&data, 0, sizeof(data)); > + > + igt_fixture > + { > + data.fd = drm_open_driver_master(DRIVER_AMDGPU); > + > + kmstest_set_vt_graphics_mode(); > + > + igt_display_require(&data.display, data.fd); > + igt_require(data.display.is_atomic); > + igt_display_require_output(&data.display); > + } > + > + igt_describe("Tests whether display scanout is triggered from MALL cache instead " > + "of GPU VRAM when screen contents are idle"); > + igt_subtest("static-screen") test_mall_ss(&data); > + > + igt_fixture > + { > + igt_display_fini(&data.display); > + } > +} > diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build > index 336acdb00..6c6166167 100644 > --- a/tests/amdgpu/meson.build > +++ b/tests/amdgpu/meson.build > @@ -34,6 +34,7 @@ if libdrm_amdgpu.found() > 'amd_vcn', > 'amd_vm', > 'amd_vrr_range', > + 'amd_mall', > ] > amdgpu_deps += libdrm_amdgpu > endif