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Wed, 15 May 2024 06:20:09 -0700 (PDT) Message-ID: Date: Wed, 15 May 2024 16:20:08 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH i-g-t v6 6/9] lib/intel_cmds_info: Introduce render tilings To: =?UTF-8?Q?Zbigniew_Kempczy=C5=84ski?= , igt-dev@lists.freedesktop.org References: <20240515121949.245280-1-zbigniew.kempczynski@intel.com> <20240515121949.245280-7-zbigniew.kempczynski@intel.com> Content-Language: en-US From: Juha-Pekka Heikkila In-Reply-To: <20240515121949.245280-7-zbigniew.kempczynski@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: juhapekka.heikkila@gmail.com Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Reviewed-by: Juha-Pekka Heikkila On 15.5.2024 15.19, Zbigniew Kempczyński wrote: > Due to hardware differences between blitter and render regarding > supported tilings and compression add new fields in cmds-info > to identify available tilings via render engine. > > Signed-off-by: Zbigniew Kempczyński > > --- > v6: Fix tilings for gen12 (JP) > --- > lib/intel_cmds_info.c | 31 +++++++++++++++++++++++++++---- > lib/intel_cmds_info.h | 6 ++++++ > 2 files changed, 33 insertions(+), 4 deletions(-) > > diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c > index e7aabf6bfb..1416e02cd4 100644 > --- a/lib/intel_cmds_info.c > +++ b/lib/intel_cmds_info.c > @@ -27,8 +27,10 @@ > #define TILE_Y BIT(T_YMAJOR) > #define TILE_Yf BIT(T_YFMAJOR) > > +#define TILE_4_64 (TILE_4 | TILE_64) > #define TILE_L_4_64 (TILE_L | TILE_4 | TILE_64) > #define TILE_L_X (TILE_L | TILE_X) > +#define TILE_L_X_4 (TILE_L | TILE_X | TILE_4) > #define TILE_L_X_Y (TILE_L | TILE_X | TILE_Y) > #define TILE_L_X_4_64 (TILE_L | TILE_X | TILE_4 | TILE_64) > #define TILE_L_Y (TILE_L | TILE_Y) > @@ -93,6 +95,23 @@ static const struct blt_cmd_info > BLT_CMD_EXTENDED); > > > +#define RENDER_TILING(_tiling, _compress_tiling) { \ > + .supported_tiling = _tiling, \ > + .supported_compressed_tiling = _compress_tiling, \ > + } > + > +static const struct render_tiling_info > + render_tiling_gen12 = RENDER_TILING(TILE_L_X_Y, TILE_Y); > + > +static const struct render_tiling_info > + render_tiling_mtl = RENDER_TILING(TILE_L_X_4_64, TILE_4); > + > +static const struct render_tiling_info > + render_tiling_dg2 = RENDER_TILING(TILE_L_X_4_64, TILE_4_64); > + > +static const struct render_tiling_info > + render_tiling_xe2 = RENDER_TILING(TILE_L_X_4_64, TILE_L_X_4_64); > + > const struct intel_cmds_info pre_gen6_cmds_info = { > .blt_cmds = { > [SRC_COPY] = &src_copy, > @@ -130,7 +149,8 @@ const struct intel_cmds_info gen12_cmds_info = { > [XY_FAST_COPY] = &gen12_xy_fast_copy, > [XY_BLOCK_COPY] = &gen12_xy_block_copy, > [XY_COLOR_BLT] = &gen6_xy_color_blt, > - } > + }, > + .render_tilings = &render_tiling_gen12, > }; > > const struct intel_cmds_info gen12_dg2_cmds_info = { > @@ -139,14 +159,16 @@ const struct intel_cmds_info gen12_dg2_cmds_info = { > [XY_FAST_COPY] = &dg2_xy_fast_copy, > [XY_BLOCK_COPY] = &dg2_xy_block_copy, > [XY_COLOR_BLT] = &gen6_xy_color_blt, > - } > + }, > + .render_tilings = &render_tiling_dg2, > }; > > const struct intel_cmds_info gen12_mtl_cmds_info = { > .blt_cmds = { > [XY_FAST_COPY] = &dg2_xy_fast_copy, > [XY_BLOCK_COPY] = &mtl_xy_block_copy, > - } > + }, > + .render_tilings = &render_tiling_mtl, > }; > > const struct intel_cmds_info gen12_pvc_cmds_info = { > @@ -164,7 +186,8 @@ const struct intel_cmds_info xe2_cmds_info = { > [XY_BLOCK_COPY] = &xe2_xy_block_copy, > [MEM_COPY] = &pvc_mem_copy, > [MEM_SET] = &pvc_mem_set, > - } > + }, > + .render_tilings = &render_tiling_xe2, > }; > > const struct blt_cmd_info *blt_get_cmd_info(const struct intel_cmds_info *cmds_info, > diff --git a/lib/intel_cmds_info.h b/lib/intel_cmds_info.h > index 0a83b6a446..6f7d655083 100644 > --- a/lib/intel_cmds_info.h > +++ b/lib/intel_cmds_info.h > @@ -43,8 +43,14 @@ struct blt_cmd_info { > #define BLT_CMD_SUPPORTS_COMPRESSION (1 << 1) > }; > > +struct render_tiling_info { > + uint32_t supported_tiling; > + uint32_t supported_compressed_tiling; > +}; > + > struct intel_cmds_info { > struct blt_cmd_info const *blt_cmds[__BLT_MAX_CMD]; > + struct render_tiling_info const *render_tilings; > }; > > extern const struct intel_cmds_info pre_gen6_cmds_info;