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[77.231.59.95]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4358e24cef3sm12633429f8f.0.2026.01.21.08.16.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Jan 2026 08:16:56 -0800 (PST) Message-ID: <1e2d0c75-35d1-4096-a96f-c3fc6f7ce52a@suse.com> Date: Wed, 21 Jan 2026 17:16:54 +0100 Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v2 4/4] stmmac: s32: enable support for Multi-IRQ mode To: jan.petrous@oss.nxp.com, Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org References: <20260121-dwmac_multi_irq-v2-0-3b829230d071@oss.nxp.com> <20260121-dwmac_multi_irq-v2-4-3b829230d071@oss.nxp.com> Content-Language: en-US, ca-ES, es-ES From: Matthias Brugger Autocrypt: addr=mbrugger@suse.com; keydata= xsFNBFP1zgUBEAC21D6hk7//0kOmsUrE3eZ55kjc9DmFPKIz6l4NggqwQjBNRHIMh04BbCMY fL3eT7ZsYV5nur7zctmJ+vbszoOASXUpfq8M+S5hU2w7sBaVk5rpH9yW8CUWz2+ZpQXPJcFa OhLZuSKB1F5JcvLbETRjNzNU7B3TdS2+zkgQQdEyt7Ij2HXGLJ2w+yG2GuR9/iyCJRf10Okq gTh//XESJZ8S6KlOWbLXRE+yfkKDXQx2Jr1XuVvM3zPqH5FMg8reRVFsQ+vI0b+OlyekT/Xe 0Hwvqkev95GG6x7yseJwI+2ydDH6M5O7fPKFW5mzAdDE2g/K9B4e2tYK6/rA7Fq4cqiAw1+u EgO44+eFgv082xtBez5WNkGn18vtw0LW3ESmKh19u6kEGoi0WZwslCNaGFrS4M7OH+aOJeqK fx5dIv2CEbxc6xnHY7dwkcHikTA4QdbdFeUSuj4YhIZ+0QlDVtS1QEXyvZbZky7ur9rHkZvP ZqlUsLJ2nOqsmahMTIQ8Mgx9SLEShWqD4kOF4zNfPJsgEMB49KbS2o9jxbGB+JKupjNddfxZ HlH1KF8QwCMZEYaTNogrVazuEJzx6JdRpR3sFda/0x5qjTadwIW6Cl9tkqe2h391dOGX1eOA 1ntn9O/39KqSrWNGvm+1raHK+Ev1yPtn0Wxn+0oy1tl67TxUjQARAQABzSRNYXR0aGlhcyBC cnVnZ2VyIDxtYnJ1Z2dlckBzdXNlLmNvbT7CwXgEEwECACIFAlV6iM0CGwMGCwkIBwMCBhUI AgkKCwQWAgMBAh4BAheAAAoJENkUC7JWEwLx6isQAIMGBgJnFWovDS7ClZtjz1LgoY8skcMU ghUZY4Z/rwwPqmMPbY8KYDdOFA+kMTEiAHOR+IyOVe2+HlMrXv/qYH4pRoxQKm8H9FbdZXgL bG8IPlBu80ZSOwWjVH+tG62KHW4RzssVrgXEFR1ZPTdbfN+9Gtf7kKxcGxWnurRJFzBEZi4s RfTSulQKqTxJ/sewOb/0kfGOJYPAt/QN5SUaWa6ILa5QFg8bLAj6bZ81CDStswDt/zJmAWp0 08NOnhrZaTQdRU7mTMddUph5YVNXEXd3ThOl8PetTyoSCt04PPTDDmyeMgB5C3INLo1AXhEp NTdu+okvD56MqCxgMfexXiqYOkEWs/wv4LWC8V8EI3Z+DQ0YuoymI5MFPsW39aPmmBhSiacx diC+7cQVQRwBR6Oz/k9oLc+0/15mc+XlbvyYfscGWs6CEeidDQyNKE/yX75KjLUSvOXYV4d4 UdaNrSoEcK/5XlW5IJNM9yae6ZOL8vZrs5u1+/w7pAlCDAAokz/As0vZ7xWiePrI+kTzuOt5 psfJOdEoMKQWWFGd/9olX5ZAyh9iXk9TQprGUOaX6sFjDrsTRycmmD9i4PdQTawObEEiAfzx 1m2MwiDs2nppsRr7qwAjyRhCq2TOAh0EDRNgYaSlbIXX/zp38FpK/9DMbtH14vVvG6FXog75 HBoOzsFNBF3VOUgBEACbvyZOfLjgfB0hg0rhlAfpTmnFwm1TjkssGZKvgMr/t6v1yGm8nmmD MIa4jblx41MSDkUKFhyB80wqrAIB6SRX0h6DOLpQrjjxbV46nxB5ANLqwektI57yenr/O+ZS +GIuiSTu1kGEbP5ezmpCYk9dxqDsAyJ+4Rx/zxlKkKGZQHdZ+UlXYOnEXexKifkTDaLne6Zc up1EgkTDVmzam4MloyrA/fAjIx2t90gfVkEEkMhZX/nc/naYq1hDQqGN778CiWkqX3qimLqj 1UsZ6qSl6qsozZxvVuOjlmafiVeXo28lEf9lPrzMG04pS3CFKU4HZsTwgOidBkI5ijbDSimI CDJ+luKPy6IjuyIETptbHZ9CmyaLgmtkGaENPqf+5iV4ZbQNFxmYTZSN56Q9ZS6Y3XeNpVm6 FOFXrlKeFTTlyFlPy9TWcBMDCKsxV5eB5kYvDGGxx26Tec1vlVKxX3kQz8o62KWsfr1kvpeu fDzx/rFpoY91XJSKAFNZz99xa7DX6eQYkM2qN9K8HuJ7XXhHTxDbxpi3wsIlFdgzVa5iWhNw iFFJdSiEaAeaHu6yXjr39FrkIVoyFPfIJVyK4d1mHe77H47WxFw6FoVbcGTEoTL6e3HDwntn OGAU6CLYcaQ4aAz1HTcDrLBzSw/BuCSAXscIuKuyE/ZT+rFbLcLwOQARAQABwsF2BBgBCAAg FiEE5rmSGMDywyUcLDoX2RQLslYTAvEFAl3VOUgCGwwACgkQ2RQLslYTAvG11w/+Mcn28jxp 0WLUdChZQoJBtl1nlkkdrIUojNT2RkT8UfPPMwNlgWBwJOzaSZRXIaWhK1elnRa10IwwHfWM GhB7nH0u0gIcSKnSKs1ebzRazI8IQdTfDH3VCQ6YMl+2bpPz4XeWqGVzcLAkamg9jsBWV6/N c0l8BNlHT5iH02E43lbDgCOxme2pArETyuuJ4tF36F7ntl1Eq1FE0Ypk5LjB602Gh2N+eOGv hnbkECywPmr7Hi5o7yh8bFOM52tKdGG+HM8KCY/sEpFRkDTA28XGNugjDyttOI4UZvURuvO6 quuvdYW4rgLVgAXgLJdQEvpnUu2j/+LjjOJBQr12ICB8T/waFc/QmUzBFQGVc20SsmAi1H9c C4XB87oE4jjc/X1jASy7JCr6u5tbZa+tZjYGPZ1cMApTFLhO4tR/a/9v1Fy3fqWPNs3F4Ra3 5irgg5jpAecT7DjFUCR/CNP5W6nywKn7MUm/19VSmj9uN484vg8w/XL49iung+Y+ZHCiSUGn LV6nybxdRG/jp8ZQdQQixPA9azZDzuTu+NjKtzIA5qtfZfmm8xC+kAwAMZ/ZnfCsKwN0bbnD YfO3B5Q131ASmu0kbwY03Mw4PhxDzZNrt4a89Y95dq5YkMtVH2Me1ZP063cFCCYCkvEAK/C8 PVrr2NoUqi/bxI8fFQJD1jVj8K0= In-Reply-To: <20260121-dwmac_multi_irq-v2-4-3b829230d071@oss.nxp.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 21/01/2026 15:23, Jan Petrous via B4 Relay wrote: > From: "Jan Petrous (OSS)" > > To get enabled Multi-IRQ mode, the driver checks: > > 1) property of 'snps,mtl-xx-config' subnode > defines 'snps,xx-queues-to-use' bigger then one, ie: > > ethernet@4033c000 { > compatible = "nxp,s32g2-dwmac"; > ... > snps,mtl-rx-config = <&mtl_rx_setup>; > ... > > mtl_rx_setup: rx-queues-config { > snps,rx-queues-to-use = <2>; > }; > > 2) queue based IRQs are set, ie: > > ethernet@4033c000 { > compatible = "nxp,s32g2-dwmac"; > ... > interrupts = , > /* CHN 0: tx, rx */ > , > , > /* CHN 1: tx, rx */ > , > ; > interrupt-names = "macirq", > "tx-queue-0", "rx-queue-0", > "tx-queue-1", "rx-queue-1"; > > If those prerequisites are met, the driver switch to Multi-IRQ mode, > using per-queue IRQs for rx/tx data pathr: > > [ 1.387045] s32-dwmac 4033c000.ethernet: Multi-IRQ mode (per queue IRQ) selected > > Now the driver owns all queues IRQs: > > root@s32g399aevb3:~# grep eth /proc/interrupts > 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac > 30: 0 0 0 0 0 0 0 0 GICv3 91 Level eth0:rx-0 > 31: 0 0 0 0 0 0 0 0 GICv3 93 Level eth0:rx-1 > 32: 0 0 0 0 0 0 0 0 GICv3 95 Level eth0:rx-2 > 33: 0 0 0 0 0 0 0 0 GICv3 97 Level eth0:rx-3 > 34: 0 0 0 0 0 0 0 0 GICv3 99 Level eth0:rx-4 > 35: 0 0 0 0 0 0 0 0 GICv3 90 Level eth0:tx-0 > 36: 0 0 0 0 0 0 0 0 GICv3 92 Level eth0:tx-1 > 37: 0 0 0 0 0 0 0 0 GICv3 94 Level eth0:tx-2 > 38: 0 0 0 0 0 0 0 0 GICv3 96 Level eth0:tx-3 > 39: 0 0 0 0 0 0 0 0 GICv3 98 Level eth0:tx-4 > > Otherwise, if one of the prerequisite don't met, the driver > continue with MAC IRQ mode: > > [ 1.387045] s32-dwmac 4033c000.ethernet: MAC IRQ mode selected > > And only MAC IRQ will be attached: > > root@s32g399aevb3:~# grep eth /proc/interrupts > 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac > > What represents the original MAC IRQ mode and is fully backward > compatible. > > Signed-off-by: Jan Petrous (OSS) Reviewed-by: Matthias Brugger > --- > drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c > index 5a485ee98fa7..823700219534 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c > @@ -2,7 +2,7 @@ > /* > * NXP S32G/R GMAC glue layer > * > - * Copyright 2019-2024 NXP > + * Copyright 2019-2026 NXP > * > */ > > @@ -149,6 +149,17 @@ static int s32_dwmac_probe(struct platform_device *pdev) > plat->core_type = DWMAC_CORE_GMAC4; > plat->pmt = 1; > plat->flags |= STMMAC_FLAG_SPH_DISABLE; > + > + /* Check for multi-IRQ config. Assumption: symetrical rx/tx queues */ > + if (plat->rx_queues_to_use > 1 && > + (res.rx_irq[0] >= 0 || res.tx_irq[0] >= 0)) { > + plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; > + dev_info(dev, "Multi-IRQ mode (per queue IRQ) selected\n"); > + } else { > + dev_info(dev, "MAC IRQ mode selected\n"); > + } > + > + plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; > plat->rx_fifo_size = 20480; > plat->tx_fifo_size = 20480; > >