Linux kernel and device drivers for NXP i.MX platforms
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From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
	devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Shawn Guo <shawnguo@kernel.org>, Li Yang <leoyang.li@nxp.com>,
	Marco Contenti <marco.c@variscite.com>,
	Nate Drude <nate.d@variscite.com>,
	FrancescoFerraro <francesco.f@variscite.com>,
	Harshesh Valera <harshesh.v@variscite.com>
Subject: Re: [PATCH v2 3/4] arm64: dts: freescale: Add support for the Variscite i.MX8MP DART8MCustomBoard
Date: Sat, 8 Jun 2024 19:49:52 +0300	[thread overview]
Message-ID: <20240608164952.GE18479@pendragon.ideasonboard.com> (raw)
In-Reply-To: <314ad280-e3e8-4087-8862-439cf45aa0f9@pengutronix.de>

Hi Ahmad,

On Mon, Nov 27, 2023 at 07:07:16AM +0100, Ahmad Fatoum wrote:
> On 25.10.23 18:50, Laurent Pinchart wrote:
> > The DT8MCustomBoard is a carrier board for DART i.MX8-based modules.
> > This device tree file adds support for the DT8MCustomBoard v2.0 with a
> > connected DART-MX8M-PLUS module.
> > 
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> 
> 
> > +&eqos {
> > +	mdio {
> > +		ethphy1: ethernet-phy@1 {
> > +			compatible = "ethernet-phy-ieee802.3-c22";
> > +			reg = <1>;
> > +			eee-broken-1000t;
> > +			reset-gpios = <&gpio_exp_2 0 GPIO_ACTIVE_LOW>;
> > +			reset-assert-us = <10000>;
> > +			reset-deassert-us = <20000>;
> 
> Ouch. So you have a PHY at address 0 (broadcast address) and a PHY at address
> 1 on the same bus? I think it's worth a comment whether broadcast for this
> PHY here is disabled by strapping or in the bootloader.

This particular PHY is an ADI1300. The schematics indicates:

LEDs - active HIGH, address 00001b
SOM PHY MDIO address 00000b

I tried to investigate, and I haven't found any mention of address 0
being a broadcast address in the ADIN1300 documentation. Trying to dig a
bit more, I've read clause 22 of the IEEE 802.3ak specification and
found this:

22.2.4.5.5 PHYAD (PHY Address)

The PHY Address is five bits, allowing 32 unique PHY addresses. The
first PHY address bit transmitted and received is the MSB of the
address. A PHY that is connected to the station management entity via
the mechanical interface defined in 22.6 shall always respond to
transactions addressed to PHY Address zero <00000>. A station management
entity that is attached to multiple PHYs must have prior knowledge of
the appropriate PHY Address for each PHY.

Section 22.6 defines a 40-pin physical connector, which is not
applicable here. I've also found
https://ieee802.org/3/10G_study/email/msg03514.html which states

"People have made all kinds of wild assumptions about the way MDIO/MDC
work in the past. Some people actually believe that PHYADD <00000> is a
broadcast address."

-- 
Regards,

Laurent Pinchart

  reply	other threads:[~2024-06-08 16:50 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-25 16:50 [PATCH v2 0/4] arm64: dts: freescale: Add Variscite i.MX8MP DART8MCustomBoard v2 Laurent Pinchart
2023-10-25 16:50 ` [PATCH v2 1/4] dt-bindings: arm: fsl: Add Variscite DT8MCustomBoard with DART MX8M-PLUS Laurent Pinchart
2023-10-25 16:50 ` [PATCH v2 2/4] arm64: dts: freescale: Add support for the Variscite DART-MX8M-PLUS SoM Laurent Pinchart
2023-11-27  5:58   ` Ahmad Fatoum
2023-11-27  6:13     ` Ahmad Fatoum
2024-06-08 16:50       ` Laurent Pinchart
2024-06-08 16:18     ` Laurent Pinchart
2023-10-25 16:50 ` [PATCH v2 3/4] arm64: dts: freescale: Add support for the Variscite i.MX8MP DART8MCustomBoard Laurent Pinchart
2023-11-27  6:07   ` Ahmad Fatoum
2024-06-08 16:49     ` Laurent Pinchart [this message]
2023-10-25 16:50 ` [PATCH v2 4/4] arm64: dts: freescale: Add panel overlay for Variscite DART Laurent Pinchart
2023-11-27  3:16   ` Shawn Guo
2024-06-08 17:43     ` Laurent Pinchart

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