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AJvYcCXPA88dmMQ4ewBqa0sbrwBV0MihmvhSv+NPob2JXTI6sxUeN5MDSbkrBjx54KgOz+3L/VO7uFlVOKgfBbWkomniezS9 X-Gm-Message-State: AOJu0YzluI2NxUr7lp0GGaVBw28N4IIiokDcnbQlYEBF+B8O3Labr7ol Bu0OhtQf0+hPEeZioHDiZlOmOyk1th/d62jiXM5KGfknqY6f8fwyZPAz+JLZoA== X-Google-Smtp-Source: AGHT+IFB5GWSyOiS5lFM4xMyeymwyJX3RWJBnJqEHBblq0QLaA5/nACE76UedKAKXnyWt2Xoaj7jKg== X-Received: by 2002:a05:6a20:b22a:b0:1bd:22fe:fcaa with SMTP id adf61e73a8af0-1bef6275a83mr1942482637.51.1719764625453; Sun, 30 Jun 2024 09:23:45 -0700 (PDT) Received: from thinkpad ([220.158.156.215]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c91ce73e34sm5028683a91.30.2024.06.30.09.23.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jun 2024 09:23:45 -0700 (PDT) Date: Sun, 30 Jun 2024 21:53:37 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v6 09/10] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Message-ID: <20240630162337.GD5264@thinkpad> References: <20240617-pci2_upstream-v6-0-e0821238f997@nxp.com> <20240617-pci2_upstream-v6-9-e0821238f997@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240617-pci2_upstream-v6-9-e0821238f997@nxp.com> On Mon, Jun 17, 2024 at 04:16:45PM -0400, Frank Li wrote: You don't need the colon after 'Call' in subject. > Invoke the common PHY API to configure mode, speed, and submode. While > these functions are optional in the PHY interface, they are necessary for > certain PHY drivers. Lack of support for these functions in a PHY driver > does not cause harm. > > Signed-off-by: Frank Li > --- > drivers/pci/controller/dwc/pci-imx6.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index ab0ed7ab3007a..18c133f5a56fc 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -30,6 +30,7 @@ > #include > #include > #include > +#include This should be moved one entry above. > #include > #include > > @@ -229,6 +230,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) > > id = imx_pcie->controller_id; > > + /* If mode_mask[0] is 0, means use phy driver to set mode */ /* If mode_mask is 0, then generic PHY driver is used to set the mode */ > + if (!drvdata->mode_mask[0]) > + return; > + > /* If mode_mask[id] is zero, means each controller have its individual gpr */ > if (!drvdata->mode_mask[id]) > id = 0; > @@ -808,6 +813,7 @@ static void imx_pcie_ltssm_enable(struct device *dev) > struct imx_pcie *imx_pcie = dev_get_drvdata(dev); > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; > > + phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB); Is this setting really universal? This looks like applicable only to specific platforms supporting this link speed. > if (drvdata->ltssm_mask) > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, > drvdata->ltssm_mask); > @@ -820,6 +826,7 @@ static void imx_pcie_ltssm_disable(struct device *dev) > struct imx_pcie *imx_pcie = dev_get_drvdata(dev); > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; > > + phy_set_speed(imx_pcie->phy, 0); > if (drvdata->ltssm_mask) > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, > drvdata->ltssm_mask, 0); > @@ -955,6 +962,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) > goto err_clk_disable; > } > > + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); > + if (ret) { > + dev_err(dev, "unable to set pcie PHY mode\n"); s/pcie/PCIe - Mani -- மணிவண்ணன் சதாசிவம்