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AJvYcCWsHeFcB4N6a70jDiJgP8ge2G/9/0EwZ1AowMNPONovkp7Lq1HcgoUXXNT73gBRB5wt0ItpAusjwFfIH/t2kGvqv0ay X-Gm-Message-State: AOJu0Ywye5ONHB7OE602n4bNDKmRy9oP3PUpQL+p6F0ATNxOv2EGHaky wMWd/E5BbqjaMvWYzfcJ73ZMM3Z8NncHWw84C7fqBdbg+dtZWiDknIRNgif2OQ== X-Google-Smtp-Source: AGHT+IFQYY74iAGQY5pOOJPCWv5JUZVONiqWh0swcBRClZ6YAaFDgYxDWJLm9Z5K35Wb0bbXsmVAGg== X-Received: by 2002:a05:690c:4441:b0:665:7184:fcd0 with SMTP id 00721157ae682-66ad8dc0d02mr32319017b3.23.1721547594246; Sun, 21 Jul 2024 00:39:54 -0700 (PDT) Received: from thinkpad ([120.56.206.118]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70d2243d137sm439633b3a.31.2024.07.21.00.39.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jul 2024 00:39:53 -0700 (PDT) Date: Sun, 21 Jul 2024 13:09:46 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Jason Liu Subject: Re: [PATCH v7 02/10] PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI Message-ID: <20240721073946.GB1908@thinkpad> References: <20240708-pci2_upstream-v7-0-ac00b8174f89@nxp.com> <20240708-pci2_upstream-v7-2-ac00b8174f89@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240708-pci2_upstream-v7-2-ac00b8174f89@nxp.com> On Mon, Jul 08, 2024 at 01:08:06PM -0400, Frank Li wrote: > From: Richard Zhu > > Correct occasional MSI triggering failures in i.MX8MP PCIe EP by applying > the correct hardware outbound alignment requirement. > > The i.MX platform has a restriction about outbound address translation. The > pci-epc-mem uses page_size to manage it. Set the correct page_size for i.MX > platform to meet the hardware requirement, which is the same as inbound > address alignment. Align it with epc_features::align. > > Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code") > Signed-off-by: Richard Zhu > Acked-by: Jason Liu > Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam - Mani > --- > drivers/pci/controller/dwc/pci-imx6.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 9a71b8aa09b3c..ca9a000c9a96d 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > > + ep->page_size = imx6_pcie->drvdata->epc_features->align; > + > ret = dw_pcie_ep_init(ep); > if (ret) { > dev_err(dev, "failed to initialize endpoint\n"); > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்