From: Frank Li <Frank.Li@nxp.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
FLATTENED DEVICE TREE BINDINGS),
imx@lists.linux.dev (open list:ARM/FREESCALE IMX / MXC ARM
ARCHITECTURE),
linux-arm-kernel@lists.infradead.org (moderated
list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE),
linux-kernel@vger.kernel.org (open list)
Cc: imx@lists.linux.dev
Subject: [PATCH 2/2] arm64: dts: imx95: add flexcan[1..5] support
Date: Mon, 5 Aug 2024 16:14:16 -0400 [thread overview]
Message-ID: <20240805201416.2974996-2-Frank.Li@nxp.com> (raw)
In-Reply-To: <20240805201416.2974996-1-Frank.Li@nxp.com>
From: Haibo Chen <haibo.chen@nxp.com>
Add the flexcan[1..5] nodes for imx95.
Reviewed-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
- CHECK_DTB warning should be fixed in linux-can-next tree.
['fsl,imx95-flexcan'] is too short
https://lore.kernel.org/imx/20240805-succinct-didactic-vicugna-e5449a-mkl@pengutronix.de/
---
arch/arm64/boot/dts/freescale/imx95.dtsi | 70 ++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index d25465c947822..7c01cfa318e7f 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -713,6 +713,34 @@ lpuart6: serial@425a0000 {
status = "disabled";
};
+ flexcan2: can@425b0000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x425b0000 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_CAN2>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
+
+ flexcan3: can@42600000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x42600000 0x10000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_CAN3>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
+
flexspi1: spi@425e0000 {
compatible = "nxp,imx8mm-fspi";
reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>;
@@ -931,6 +959,34 @@ mu8: mailbox@42730000 {
#mbox-cells = <2>;
status = "disabled";
};
+
+ flexcan4: can@427c0000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x427c0000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_CAN4>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
+
+ flexcan5: can@427d0000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x427d0000 0x10000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_CAN5>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
};
aips3: bus@42800000 {
@@ -1205,6 +1261,20 @@ lpuart2: serial@44390000 {
status = "disabled";
};
+ flexcan1: can@443a0000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x443a0000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSAON>,
+ <&scmi_clk IMX95_CLK_CAN1>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
+
sai1: sai@443b0000 {
compatible = "fsl,imx95-sai";
reg = <0x443b0000 0x10000>;
--
2.34.1
next prev parent reply other threads:[~2024-08-05 20:14 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-05 20:14 [PATCH 1/2] arm64: dts: imx95: add DDR Perf Monitor node Frank Li
2024-08-05 20:14 ` Frank Li [this message]
2024-08-13 7:31 ` Shawn Guo
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