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AJvYcCXz4jO9RK25RTErrxsMdf1kchTZXBb1GLAqTIQGwFqCgh57o0JkhGcTKDok55sJVZJqy3I=@lists.linux.dev X-Gm-Message-State: AOJu0YxIiyiv4zFBxHpckou/mn/mHPi2mNWulfwHjYtv8sNabOrKkf7N OJaWGpB7du0brL5pQ/KFjuhO2Zs8uBvh8vog4BxmeTbnXVlrjo5UVRrrYUpWTg== X-Google-Smtp-Source: AGHT+IFlXu8G84DVRp5SNbsxFjbfXP/Dw/Xcx3dm3n7P1qn/jaVoagoGhBzzqVVH6hqorkyr3amAiw== X-Received: by 2002:a05:6a00:4f88:b0:70d:3777:da8b with SMTP id d2e1a72fcca58-717458a9cfamr16603380b3a.25.1725550076860; Thu, 05 Sep 2024 08:27:56 -0700 (PDT) Received: from thinkpad ([120.60.52.248]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7178c66839dsm1508852b3a.15.2024.09.05.08.27.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 08:27:56 -0700 (PDT) Date: Thu, 5 Sep 2024 20:57:42 +0530 From: Manivannan Sadhasivam To: Johan Hovold Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Jingoo Han , Chuanhua Lei , Marek Vasut , Yoshihiro Shimoda , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, abel.vesa@linaro.org, johan+linaro@kernel.org, Shashank Babu Chinta Venkata Subject: Re: [PATCH v6 3/4] PCI: qcom: Add equalization settings for 16.0 GT/s Message-ID: <20240905152742.4llkcjvvu3klmo6j@thinkpad> References: <20240904-pci-qcom-gen4-stability-v6-0-ec39f7ae3f62@linaro.org> <20240904-pci-qcom-gen4-stability-v6-3-ec39f7ae3f62@linaro.org> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Sep 04, 2024 at 11:39:09AM +0200, Johan Hovold wrote: > On Wed, Sep 04, 2024 at 12:41:59PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > > From: Shashank Babu Chinta Venkata > > > > During high data transmission rates such as 16.0 GT/s, there is an > > increased risk of signal loss due to poor channel quality and interference. > > This can impact receiver's ability to capture signals accurately. Hence, > > signal compensation is achieved through appropriate lane equalization > > settings at both transmitter and receiver. This will result in increased > > PCIe signal strength. > > > > Signed-off-by: Shashank Babu Chinta Venkata > > Reviewed-by: Manivannan Sadhasivam > > [mani: dropped the code refactoring and minor changes] > > Signed-off-by: Manivannan Sadhasivam [...] > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h > > new file mode 100644 > > index 000000000000..259e04b7bdf9 > > --- /dev/null > > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h > > @@ -0,0 +1,8 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > > + */ > > + > > +#include "pcie-designware.h" > > You only need a forward declaration: > > struct dw_pcie; > > > + > > +void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci); > > Compile guard still missing. > Perhaps we can just get rid of the Kconfig entry and build it by default for both RC and EP drivers? I don't see a value in building it as a separate module. And we may also move more common code in the future. - Mani -- மணிவண்ணன் சதாசிவம்