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AJvYcCUeRVwN6NI326WkaM3Let7fVfu+9BfS8xuRt+R9xOlgq+43k5hG7DEw7S9vi/+tBh8fvHI=@lists.linux.dev X-Gm-Message-State: AOJu0YwaBoLF1gikT6xykxrtae4EZzQP05jviKIfPzIcdpqVvvY1L7FC uKsOwznwvuCGUFz0pOFSGAXYB07lU8lvbrT4/Ex9cCSghJohrdX5bajuo6+cTQ== X-Google-Smtp-Source: AGHT+IEFhMlMl+SifAdPrVg99u83uazLX/A9KcHRvv7Tuv35akUo2976i/YilQVOuBqYd19nUmnDHQ== X-Received: by 2002:a17:902:da85:b0:20b:6f04:486f with SMTP id d9443c01a7336-20e9489afa8mr44178795ad.18.1729617666017; Tue, 22 Oct 2024 10:21:06 -0700 (PDT) Received: from thinkpad ([36.255.17.224]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7eeef535sm45591245ad.44.2024.10.22.10.21.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 10:21:05 -0700 (PDT) Date: Tue, 22 Oct 2024 22:50:59 +0530 From: Manivannan Sadhasivam To: Richard Zhu Cc: kw@linux.com, bhelgaas@google.com, lpieralisi@kernel.org, frank.li@nxp.com, l.stach@pengutronix.de, robh+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, krzysztof.kozlowski+dt@linaro.org, festevam@gmail.com, s.hauer@pengutronix.de, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: Re: [PATCH v4 9/9] arm64: dts: imx95: Add ref clock for i.MX95 PCIe Message-ID: <20241022172059.wuw5xel7m4vobarq@thinkpad> References: <1728981213-8771-1-git-send-email-hongxing.zhu@nxp.com> <1728981213-8771-10-git-send-email-hongxing.zhu@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1728981213-8771-10-git-send-email-hongxing.zhu@nxp.com> On Tue, Oct 15, 2024 at 04:33:33PM +0800, Richard Zhu wrote: > Add ref clock for i.MX95 PCIe. > > Signed-off-by: Richard Zhu > Reviewed-by: Frank Li > --- > arch/arm64/boot/dts/freescale/imx95.dtsi | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi > index 03661e76550f..5cb504b5f851 100644 > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi > @@ -1473,6 +1473,14 @@ smmu: iommu@490d0000 { > }; > }; > > + hsio_blk_ctl: syscon@4c0100c0 { > + compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; > + reg = <0x0 0x4c0100c0 0x0 0x4>; > + #clock-cells = <1>; > + clocks = <&dummy>; > + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; > + }; This is an internal reference clock, right? Please mention it in patch description since the controller supports external reference clock also. - Mani > + > pcie0: pcie@4c300000 { > compatible = "fsl,imx95-pcie"; > reg = <0 0x4c300000 0 0x10000>, > @@ -1500,8 +1508,9 @@ pcie0: pcie@4c300000 { > clocks = <&scmi_clk IMX95_CLK_HSIO>, > <&scmi_clk IMX95_CLK_HSIOPLL>, > <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, > - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; > - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; > + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, > + <&hsio_blk_ctl 0>; > + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; > assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, > <&scmi_clk IMX95_CLK_HSIOPLL>, > <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; > @@ -1528,8 +1537,9 @@ pcie0_ep: pcie-ep@4c300000 { > clocks = <&scmi_clk IMX95_CLK_HSIO>, > <&scmi_clk IMX95_CLK_HSIOPLL>, > <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, > - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; > - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; > + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, > + <&hsio_blk_ctl 0>; > + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; > assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, > <&scmi_clk IMX95_CLK_HSIOPLL>, > <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; > -- > 2.37.1 > -- மணிவண்ணன் சதாசிவம்