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AJvYcCWyItAYJMEPKjDK18kcRtDYpOMr6Duuk5gtHCy64VSwEyvleX5JlBwzp0LlCNLJDPXGPJE=@lists.linux.dev X-Gm-Message-State: AOJu0YyuJBCDs+kJ8qer6pUA+1bYHEIx45Q928JILInFRqYii3Zuv8eB 4pb7+yTroNauEsJuV9nRbMBRe6KdghCFoYknHNA0GD/X5+Yh3JTbt87yfNobfA== X-Google-Smtp-Source: AGHT+IF6oNS7zAaqiMj3qBtazoexGSI49TeW8s00tlEKm6P+2kEMfwF3rimz60UqsKAumxJWheQLUg== X-Received: by 2002:a05:6830:2a8f:b0:718:a3e:29b7 with SMTP id 46e09a7af769-71a779213bamr15070132a34.7.1732007830619; Tue, 19 Nov 2024 01:17:10 -0800 (PST) Received: from thinkpad ([117.213.96.14]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7f8c1dade0esm7241941a12.66.2024.11.19.01.17.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 01:17:10 -0800 (PST) Date: Tue, 19 Nov 2024 14:46:59 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Bjorn Helgaas , Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, alyssa@rosenzweig.io, bpf@vger.kernel.org, broonie@kernel.org, jgg@ziepe.ca, joro@8bytes.org, lgirdwood@gmail.com, maz@kernel.org, p.zabel@pengutronix.de, robin.murphy@arm.com, will@kernel.org Subject: Re: [PATCH v5 2/2] PCI: imx6: Add IOMMU and ITS MSI support for i.MX95 Message-ID: <20241119091659.rmdufvdi6jkynvfe@thinkpad> References: <20241104-imx95_lut-v5-0-feb972f3f13b@nxp.com> <20241104-imx95_lut-v5-2-feb972f3f13b@nxp.com> <20241113174841.olnyu5l6rbmr3tqh@thinkpad> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Nov 13, 2024 at 01:09:57PM -0500, Frank Li wrote: [...] > > > + for (i = 0; i < IMX95_MAX_LUT; i++) { > > > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); > > > + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); > > > + > > > + if (!(data1 & IMX95_PE0_LUT_VLD)) { > > > + if (free < 0) > > > + free = i; > > > > So you don't increment 'free' once it becomes >=0? Why can't you use the loop > > iterator 'i' itself instead of 'free'? > > It is used to find first free slot. This loop check if there are duplicated > entry. If no duplicated rid entry, then use first free slot. > Ah, so you have combined both in one loop. A comment on top would've been helpful to understand the logic. [...] > > > + if (!err_i) > > > + return imx_pcie_add_lut(imx_pcie, rid, sid_i); > > > + else if (!err_m) > > > + /* Hardware auto add 2 bit controller id ahead of stream ID */ > > > > What is this comment for? I don't find it relevant here. > > The comment for why need mask 2bits before config lut. for example, dts > set stream id is 0xC4, but lut only need 0x4. > Ok. It was not super clear. Could you please reword it as below? "LUT only needs the lower 6 bits of the SID as it will prepend the 2 bit controller ID by default." - Mani -- மணிவண்ணன் சதாசிவம்