From: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>
To: Chester Lin <chester62515@gmail.com>,
Matthias Brugger <mbrugger@suse.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
NXP S32 Linux <s32@nxp.com>, Christophe Lizzi <clizzi@redhat.com>,
Alberto Ruiz <aruizrui@redhat.com>,
Enric Balletbo <eballetb@redhat.com>,
Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Subject: [PATCH v4 2/4] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
Date: Fri, 20 Dec 2024 14:39:14 +0200 [thread overview]
Message-ID: <20241220123916.1452582-3-ciprianmarian.costea@oss.nxp.com> (raw)
In-Reply-To: <20241220123916.1452582-1-ciprianmarian.costea@oss.nxp.com>
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
With respect to S32G2/S32G3 SoC based boards, there are multiple RDB
(rdb2 vs rdb3) and EVB (for G2 vs for G3) board revisions. These versions
are quite similar. The common part for the EVB revisions will be
centralized in 's32gxxa-evb.dtsi' file, while the RDB commonalities will
be placed in 's32gxxa-rdb.dtsi' file.
This refactor will also serve for other modules in the future, such as
FlexCAN, DSPI.
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
.../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
.../boot/dts/freescale/s32gxxxa-rdb.dtsi | 122 ++++++++++++++
2 files changed, 272 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
new file mode 100644
index 000000000000..a44eff28073a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright 2024 NXP
+ *
+ * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
+ * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
+ * Larisa Grigore <larisa.grigore@nxp.com>
+ */
+
+&pinctrl {
+ i2c0_pins: i2c0-pins {
+ i2c0-grp0 {
+ pinmux = <0x101>, <0x111>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-grp1 {
+ pinmux = <0x2352>, <0x2362>;
+ };
+ };
+
+ i2c0_gpio_pins: i2c0-gpio-pins {
+ i2c0-gpio-grp0 {
+ pinmux = <0x100>, <0x110>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-gpio-grp1 {
+ pinmux = <0x2350>, <0x2360>;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ i2c1-grp0 {
+ pinmux = <0x131>, <0x141>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c1-grp1 {
+ pinmux = <0x2cd2>, <0x2ce2>;
+ };
+ };
+
+ i2c1_gpio_pins: i2c1-gpio-pins {
+ i2c1-gpio-grp0 {
+ pinmux = <0x130>, <0x140>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c1-gpio-grp1 {
+ pinmux = <0x2cd0>, <0x2ce0>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ i2c2-grp0 {
+ pinmux = <0x151>, <0x161>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c2-grp1 {
+ pinmux = <0x2cf2>, <0x2d02>;
+ };
+ };
+
+ i2c2_gpio_pins: i2c2-gpio-pins {
+ i2c2-gpio-grp0 {
+ pinmux = <0x150>, <0x160>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c2-gpio-grp1 {
+ pinmux = <0x2cf0>, <0x2d00>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ i2c4-grp0 {
+ pinmux = <0x211>, <0x222>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-grp1 {
+ pinmux = <0x2d43>, <0x2d33>;
+ };
+ };
+
+ i2c4_gpio_pins: i2c4-gpio-pins {
+ i2c4-gpio-grp0 {
+ pinmux = <0x210>, <0x220>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-gpio-grp1 {
+ pinmux = <0x2d40>, <0x2d30>;
+ };
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-1 = <&i2c0_gpio_pins>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-1 = <&i2c1_gpio_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&i2c2_gpio_pins>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&i2c4_gpio_pins>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
new file mode 100644
index 000000000000..91fd8dbf2224
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright 2024 NXP
+ *
+ * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
+ * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
+ * Larisa Grigore <larisa.grigore@nxp.com>
+ */
+
+&pinctrl {
+ i2c0_pins: i2c0-pins {
+ i2c0-grp0 {
+ pinmux = <0x1f2>, <0x201>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-grp1 {
+ pinmux = <0x2353>, <0x2363>;
+ };
+ };
+
+ i2c0_gpio_pins: i2c0-gpio-pins {
+ i2c0-gpio-grp0 {
+ pinmux = <0x1f0>, <0x200>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-gpio-grp1 {
+ pinmux = <0x2350>, <0x2360>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ i2c2-grp0 {
+ pinmux = <0x151>, <0x161>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c2-grp1 {
+ pinmux = <0x2cf2>, <0x2d02>;
+ };
+ };
+
+ i2c2_gpio_pins: i2c2-gpio-pins {
+ i2c2-gpio-grp0 {
+ pinmux = <0x2cf0>, <0x2d00>;
+ };
+
+ i2c2-gpio-grp1 {
+ pinmux = <0x150>, <0x160>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ i2c4-grp0 {
+ pinmux = <0x211>, <0x222>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-grp1 {
+ pinmux = <0x2d43>, <0x2d33>;
+ };
+ };
+
+ i2c4_gpio_pins: i2c4-gpio-pins {
+ i2c4-gpio-grp0 {
+ pinmux = <0x210>, <0x220>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-gpio-grp1 {
+ pinmux = <0x2d40>, <0x2d30>;
+ };
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-1 = <&i2c0_gpio_pins>;
+ status = "okay";
+
+ pcal6524: gpio-expander@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&i2c2_gpio_pins>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&i2c4_gpio_pins>;
+ status = "okay";
+};
--
2.45.2
next prev parent reply other threads:[~2024-12-20 12:39 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-20 12:39 [PATCH v4 0/4] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Costea
2024-12-20 12:39 ` [PATCH v4 1/4] arm64: dts: s32g: add 'I2C' common board support Ciprian Costea
2024-12-20 15:44 ` Frank Li
2025-01-13 9:15 ` Ciprian Marian Costea
2024-12-20 12:39 ` Ciprian Costea [this message]
2024-12-20 16:02 ` [PATCH v4 2/4] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' " Frank Li
2025-01-13 9:56 ` Ciprian Marian Costea
2024-12-20 12:39 ` [PATCH v4 3/4] arm64: dts: s32g: include necessary 'EVB/RDB' common board dtsi Ciprian Costea
2024-12-20 12:39 ` [PATCH v4 4/4] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4 Ciprian Costea
2024-12-20 15:55 ` Frank Li
2025-01-13 9:59 ` Ciprian Marian Costea
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