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[75.72.162.184]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4796edc29ccsm99746291cf.77.2025.04.15.18.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 18:01:57 -0700 (PDT) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Cc: aford@beaconembedded.com, Frank.li@nxp.com, Adam Ford , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH V2 06/10] arm64: dts: imx8mm-beacon: Configure Ethernet PHY reset and GPIO IRQ Date: Tue, 15 Apr 2025 20:01:32 -0500 Message-ID: <20250416010141.1785841-6-aford173@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250416010141.1785841-1-aford173@gmail.com> References: <20250416010141.1785841-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Ethernet PHY setup currently assumes that the bootloader will take the PHY out of reset, but this behavior is not guaranteed across all bootloaders. Add the reset GPIO to ensure the kernel can properly control the PHY reset line. Also configure the PHY IRQ GPIO to enable interrupt-driven link status reporting, instead of relying on polling. This ensures more reliable Ethernet initialization and improves PHY event handling. Signed-off-by: Adam Ford --- V2: Update commit message. No active changes. arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 9ba0cb89fa24..ed7a1be4a1a6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -78,6 +78,9 @@ mdio { ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -315,6 +318,7 @@ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; }; -- 2.48.1