From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBE7017A30C for ; Thu, 17 Apr 2025 13:03:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.194.8.81 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744895039; cv=none; b=SNkr67hofY3t1abj7Uv3pm/7szg9bEZVhGmF/Umhc9/P+xaRQCoLzEQskS47d94UEKr0K7DlgjgO60Ck+y3jyFaY1IzeliJy3ma1J/58Znv3mFN/nwFwvLcoEalCZfaRIub7gU31LU2dYn7onremtsag9BEsZhat/rC2WIK0DWM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744895039; c=relaxed/simple; bh=lFeALokJFpgk28Aq35eQ1HRQJYe1F50kbXfYETsPyFI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=GNPAUdVI6RhYJ35rLLoL0Qu12cBhgmxWFsNWHd1R+NHaIhtr96xFDpB4GLxgfwhbwWsIcpb3TOo/V/zt2b/iUx50sMZ4EEu6afKcHHdy5mbJB2SgbYkM/giMsosKPHYgejxSDgEM1Z0+3lF2wkQ3hwh539m+n3HhS8uFzSbh788= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it; spf=pass smtp.mailfrom=dolcini.it; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b=KPzhyH1W; arc=none smtp.client-ip=217.194.8.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dolcini.it Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b="KPzhyH1W" Received: from francesco-nb (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id B71961F91A; Thu, 17 Apr 2025 15:03:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dolcini.it; s=default; t=1744895028; bh=LVIv+Euugq4tGgOroUBB26lcmJe4QB+yarX/KrXGKoU=; h=From:To:Subject; b=KPzhyH1WrJIKuXn4iDgsC61lXzCe1axXYyM9GRAGE4fsHLHTnE1wAqWGZwfS71ft/ nA0ZpkIoMNpVG8On6N+KDyb5ttYOEERQ4IWBTolo/A2cjwB/nhLdB/CGaqiQTlf2OM /gSGRJDD8Lr6PSKZjNK8AXLJc4ZqSVQL+V4GkMC53obPRlvHHWgipM4GR0I5+mSGbn KKWmuEsMXuXmzbktwZlDCWTdCsFzXyFe1GnOUP9uJpdLcctRzzgN5bxc/+20wDuU9Y vBNiWRRq3YA0jxNMExpISjRCEOFuqgp+vByQIX6uAk0qLQmmvjCyVM70p9tEU552pe wsPG/35PlJDAA== Date: Thu, 17 Apr 2025 15:03:42 +0200 From: Francesco Dolcini To: Wojciech Dubowik Cc: linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org Subject: Re: [PATCH] arm64: dts: imx8mm-verdin: Link reg_nvcc_sd to usdhc2 Message-ID: <20250417130342.GA18817@francesco-nb> References: <20250417112012.785420-1-Wojciech.Dubowik@mt.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250417112012.785420-1-Wojciech.Dubowik@mt.com> Hello Wojciech, thanks very much for your patch. On Thu, Apr 17, 2025 at 01:20:11PM +0200, Wojciech Dubowik wrote: > Link LDO5 labeled reg_nvcc_sd from PMIC to align with > hardware configuration specified in the datasheet. > > Without this definition LDO5 will be powered down, disabling > SD card after bootup. This has been introduced in commit > f5aab0438ef1 (regulator: pca9450: Fix enable register for LDO5). > > Fixes: f5aab0438ef1 (regulator: pca9450: Fix enable register for LDO5) > Cc: stable@vger.kernel.org > > Signed-off-by: Wojciech Dubowik > --- > arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > index 7251ad3a0017..6307c5caf3bc 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > @@ -785,6 +785,7 @@ &usdhc2 { > pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; > pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; > vmmc-supply = <®_usdhc2_vmmc>; > + vqmmc-supply = <®_nvcc_sd>; I am worried just doing this will have some side effects. Before this patch, the switch between 1v8 and 3v3 was done because we have a GPIO, connected to the PMIC, controlled by the USDHC2 instance (MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT, see pinctrl_usdhc2). With your change both the PMIC will be programmed with a different voltage over i2c and the GPIO will also toggle. It does not sound like what we want to do. Maybe we should have a "regulator-gpio" with vin-supply = <®_nvcc_sd>, as we recently did here https://lore.kernel.org/all/20250414123827.428339-1-ivitro@gmail.com/T/#m2964f1126a6732a66a6e704812f2b786e8237354 ? Francesco