[PATCH 1/1] dt-bindings: interrupt-controller: Add arm,armv7m-nvic and fix #interrupt-cells

[Frank Li <Frank.Li@nxp.com>]

According to existed dts arch/arm/boot/dts/armv7-m.dtsi, compatible string
should be arm,armv7m-nvic, #interrupt-cells is 1 and
arm,num-irq-priority-bits is optional property.

Fix below CHECK_DTB warning:

arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dtb: /interrupt-controller@e000e100:
    failed to match any schema with compatible: ['arm,armv7m-nvic']

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 .../devicetree/bindings/interrupt-controller/arm,nvic.yaml  | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml
index d89eca956c5fa..a08632804d052 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml
@@ -17,6 +17,7 @@ description:
 properties:
   compatible:
     enum:
+      - arm,armv7m-nvic
       - arm,v6m-nvic
       - arm,v7m-nvic
       - arm,v8m-nvic
@@ -30,10 +31,10 @@ properties:
   interrupt-controller: true
 
   '#interrupt-cells':
-    const: 2
+    const: 1
     description: |
       Number of cells to encode an interrupt source:
-      first = interrupt number, second = priority.
+      first = interrupt number.
 
   arm,num-irq-priority-bits:
     description: Number of priority bits implemented by the SoC
@@ -45,7 +46,6 @@ required:
   - reg
   - interrupt-controller
   - '#interrupt-cells'
-  - arm,num-irq-priority-bits
 
 additionalProperties: false
 
-- 
2.34.1