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Add register existence bits to detect invalid register access when using different versions of the CSI2 controller. No functional change. Signed-off-by: Frank Li --- drivers/staging/media/imx/imx6-mipi-csi2.c | 165 +++++++++++++++++------------ 1 file changed, 96 insertions(+), 69 deletions(-) diff --git a/drivers/staging/media/imx/imx6-mipi-csi2.c b/drivers/staging/media/imx/imx6-mipi-csi2.c index 54e9491d3428686288a5bc9bb58a5a0a25aca696..b04c1b98c088b8bfa66eb3f61cca8bb735b7eae4 100644 --- a/drivers/staging/media/imx/imx6-mipi-csi2.c +++ b/drivers/staging/media/imx/imx6-mipi-csi2.c @@ -34,12 +34,30 @@ */ #define CSI2_DEFAULT_MAX_MBPS 849 +struct dw_csi2_regs { + u32 version; + u32 n_lanes; + u32 phy_shutdownz; + u32 dphy_rstz; + u32 resetn; + u32 phy_state; + u32 data_ids_1; + u32 data_ids_2; + u32 err1; + u32 err2; + u32 msk1; + u32 msk2; + u32 phy_tst_ctrl0; + u32 phy_tst_ctrl1; +}; + struct csi2_dev { struct device *dev; struct v4l2_subdev sd; struct v4l2_async_notifier notifier; struct media_pad pad[CSI2_NUM_PADS]; void __iomem *base; + const struct dw_csi2_regs *regs; struct clk_bulk_data *clks; int num_clks; @@ -60,28 +78,53 @@ struct csi2_dev { #define DEVICE_NAME "imx6-mipi-csi2" -/* Register offsets */ -#define CSI2_VERSION 0x000 -#define CSI2_N_LANES 0x004 -#define CSI2_PHY_SHUTDOWNZ 0x008 -#define CSI2_DPHY_RSTZ 0x00c -#define CSI2_RESETN 0x010 -#define CSI2_PHY_STATE 0x014 +/* Help check wrong access unexisted register at difference IP version */ +#define DW_REG_EXIST 0x80000000 +#define DW_REG(x) (DW_REG_EXIST | (x)) + +/* Register offsets for v0 */ +static const struct dw_csi2_regs dw_csi2_v0 = { + .version = DW_REG(0x0), + .n_lanes = DW_REG(0x4), + .phy_shutdownz = DW_REG(0x8), + .dphy_rstz = DW_REG(0xc), + .resetn = DW_REG(0x10), + .phy_state = DW_REG(0x14), + .data_ids_1 = DW_REG(0x18), + .data_ids_2 = DW_REG(0x1c), + .err1 = DW_REG(0x20), + .err2 = DW_REG(0x24), + .msk1 = DW_REG(0x28), + .msk2 = DW_REG(0x2c), + .phy_tst_ctrl0 = DW_REG(0x30), + .phy_tst_ctrl1 = DW_REG(0x34), +}; + +static int dw_csi2_reg_err(struct csi2_dev *csi2, const char *name) +{ + dev_err_once(csi2->dev, "access to unexisted register: %s", name); + return 0; +} + +#define dw_reg_exist(csi2, __name) ((csi2)->regs->__name & DW_REG_EXIST) + +#define dw_writel(csi2, value, __name) (dw_reg_exist((csi2), __name) ? \ +writel(value, (csi2)->base + (csi2->regs->__name & ~DW_REG_EXIST)) : \ +dw_csi2_reg_err((csi2), #__name)) + +#define dw_readl(csi2, __name) (dw_reg_exist((csi2), __name) ? \ +readl((csi2)->base + ((csi2)->regs->__name & ~DW_REG_EXIST)) : \ +dw_csi2_reg_err(csi2, #__name)) + #define PHY_STOPSTATEDATA_BIT 4 #define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n)) #define PHY_RXCLKACTIVEHS BIT(8) #define PHY_RXULPSCLKNOT BIT(9) #define PHY_STOPSTATECLK BIT(10) -#define CSI2_DATA_IDS_1 0x018 -#define CSI2_DATA_IDS_2 0x01c -#define CSI2_ERR1 0x020 -#define CSI2_ERR2 0x024 -#define CSI2_MSK1 0x028 -#define CSI2_MSK2 0x02c -#define CSI2_PHY_TST_CTRL0 0x030 + #define PHY_TESTCLR BIT(0) #define PHY_TESTCLK BIT(1) -#define CSI2_PHY_TST_CTRL1 0x034 + #define PHY_TESTEN BIT(16) /* * i.MX CSI2IPU Gasket registers follow. The CSI2IPU gasket is @@ -132,42 +175,42 @@ static inline struct csi2_dev *notifier_to_dev(struct v4l2_async_notifier *n) static void csi2_enable(struct csi2_dev *csi2, bool enable) { if (enable) { - writel(0x1, csi2->base + CSI2_PHY_SHUTDOWNZ); - writel(0x1, csi2->base + CSI2_DPHY_RSTZ); - writel(0x1, csi2->base + CSI2_RESETN); + dw_writel(csi2, 0x1, phy_shutdownz); + dw_writel(csi2, 0x1, dphy_rstz); + dw_writel(csi2, 0x1, resetn); } else { - writel(0x0, csi2->base + CSI2_PHY_SHUTDOWNZ); - writel(0x0, csi2->base + CSI2_DPHY_RSTZ); - writel(0x0, csi2->base + CSI2_RESETN); + dw_writel(csi2, 0x0, phy_shutdownz); + dw_writel(csi2, 0x0, dphy_rstz); + dw_writel(csi2, 0x0, resetn); } } static void csi2_set_lanes(struct csi2_dev *csi2, unsigned int lanes) { - writel(lanes - 1, csi2->base + CSI2_N_LANES); + dw_writel(csi2, lanes - 1, n_lanes); } static void dw_mipi_csi2_phy_write(struct csi2_dev *csi2, u32 test_code, u32 test_data) { /* Clear PHY test interface */ - writel(PHY_TESTCLR, csi2->base + CSI2_PHY_TST_CTRL0); - writel(0x0, csi2->base + CSI2_PHY_TST_CTRL1); - writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0); + dw_writel(csi2, PHY_TESTCLR, phy_tst_ctrl0); + dw_writel(csi2, 0x0, phy_tst_ctrl1); + dw_writel(csi2, 0x0, phy_tst_ctrl0); /* Raise test interface strobe signal */ - writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0); + dw_writel(csi2, PHY_TESTCLK, phy_tst_ctrl0); /* Configure address write on falling edge and lower strobe signal */ - writel(PHY_TESTEN | test_code, csi2->base + CSI2_PHY_TST_CTRL1); - writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0); + dw_writel(csi2, PHY_TESTEN | test_code, phy_tst_ctrl1); + dw_writel(csi2, 0x0, phy_tst_ctrl0); /* Configure data write on rising edge and raise strobe signal */ - writel(test_data, csi2->base + CSI2_PHY_TST_CTRL1); - writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0); + dw_writel(csi2, test_data, phy_tst_ctrl1); + dw_writel(csi2, PHY_TESTCLK, phy_tst_ctrl0); /* Clear strobe signal */ - writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0); + dw_writel(csi2, 0x0, phy_tst_ctrl0); } /* @@ -233,16 +276,15 @@ static int __maybe_unused csi2_dphy_wait_ulp(struct csi2_dev *csi2) int ret; /* wait for ULP on clock lane */ - ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg, - !(reg & PHY_RXULPSCLKNOT), 0, 500000); + ret = read_poll_timeout(dw_readl, reg, !(reg & PHY_RXULPSCLKNOT), + 0, 500000, 0, csi2, phy_state); if (ret) { v4l2_err(&csi2->sd, "ULP timeout, phy_state = 0x%08x\n", reg); return ret; } /* wait until no errors on bus */ - ret = readl_poll_timeout(csi2->base + CSI2_ERR1, reg, - reg == 0x0, 0, 500000); + ret = read_poll_timeout(dw_readl, reg, reg == 0x0, 0, 500000, 0, csi2, err1); if (ret) { v4l2_err(&csi2->sd, "stable bus timeout, err1 = 0x%08x\n", reg); return ret; @@ -259,8 +301,7 @@ static void csi2_dphy_wait_stopstate(struct csi2_dev *csi2, unsigned int lanes) mask = PHY_STOPSTATECLK | (((1 << lanes) - 1) << PHY_STOPSTATEDATA_BIT); - ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg, - (reg & mask) == mask, 0, 500000); + ret = read_poll_timeout(dw_readl, reg, (reg & mask) == mask, 0, 500000, 0, csi2, phy_state); if (ret) { v4l2_warn(&csi2->sd, "LP-11 wait timeout, likely a sensor driver bug, expect capture failures.\n"); v4l2_warn(&csi2->sd, "phy_state = 0x%08x\n", reg); @@ -273,8 +314,8 @@ static int csi2_dphy_wait_clock_lane(struct csi2_dev *csi2) u32 reg; int ret; - ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg, - (reg & PHY_RXCLKACTIVEHS), 0, 500000); + ret = read_poll_timeout(dw_readl, reg, (reg & PHY_RXCLKACTIVEHS), + 0, 500000, 0, csi2, phy_state); if (ret) { v4l2_err(&csi2->sd, "clock lane timeout, phy_state = 0x%08x\n", reg); @@ -556,34 +597,20 @@ static int csi2_log_status(struct v4l2_subdev *sd) struct csi2_dev *csi2 = sd_to_dev(sd); v4l2_info(sd, "-----MIPI CSI status-----\n"); - v4l2_info(sd, "VERSION: 0x%x\n", - readl(csi2->base + CSI2_VERSION)); - v4l2_info(sd, "N_LANES: 0x%x\n", - readl(csi2->base + CSI2_N_LANES)); - v4l2_info(sd, "PHY_SHUTDOWNZ: 0x%x\n", - readl(csi2->base + CSI2_PHY_SHUTDOWNZ)); - v4l2_info(sd, "DPHY_RSTZ: 0x%x\n", - readl(csi2->base + CSI2_DPHY_RSTZ)); - v4l2_info(sd, "RESETN: 0x%x\n", - readl(csi2->base + CSI2_RESETN)); - v4l2_info(sd, "PHY_STATE: 0x%x\n", - readl(csi2->base + CSI2_PHY_STATE)); - v4l2_info(sd, "DATA_IDS_1: 0x%x\n", - readl(csi2->base + CSI2_DATA_IDS_1)); - v4l2_info(sd, "DATA_IDS_2: 0x%x\n", - readl(csi2->base + CSI2_DATA_IDS_2)); - v4l2_info(sd, "ERR1: 0x%x\n", - readl(csi2->base + CSI2_ERR1)); - v4l2_info(sd, "ERR2: 0x%x\n", - readl(csi2->base + CSI2_ERR2)); - v4l2_info(sd, "MSK1: 0x%x\n", - readl(csi2->base + CSI2_MSK1)); - v4l2_info(sd, "MSK2: 0x%x\n", - readl(csi2->base + CSI2_MSK2)); - v4l2_info(sd, "PHY_TST_CTRL0: 0x%x\n", - readl(csi2->base + CSI2_PHY_TST_CTRL0)); - v4l2_info(sd, "PHY_TST_CTRL1: 0x%x\n", - readl(csi2->base + CSI2_PHY_TST_CTRL1)); + v4l2_info(sd, "VERSION: 0x%x\n", dw_readl(csi2, version)); + v4l2_info(sd, "N_LANES: 0x%x\n", dw_readl(csi2, n_lanes)); + v4l2_info(sd, "PHY_SHUTDOWNZ: 0x%x\n", dw_readl(csi2, phy_shutdownz)); + v4l2_info(sd, "DPHY_RSTZ: 0x%x\n", dw_readl(csi2, dphy_rstz)); + v4l2_info(sd, "RESETN: 0x%x\n", dw_readl(csi2, resetn)); + v4l2_info(sd, "PHY_STATE: 0x%x\n", dw_readl(csi2, phy_state)); + v4l2_info(sd, "DATA_IDS_1: 0x%x\n", dw_readl(csi2, data_ids_1)); + v4l2_info(sd, "DATA_IDS_2: 0x%x\n", dw_readl(csi2, data_ids_2)); + v4l2_info(sd, "ERR1: 0x%x\n", dw_readl(csi2, err1)); + v4l2_info(sd, "ERR2: 0x%x\n", dw_readl(csi2, err2)); + v4l2_info(sd, "MSK1: 0x%x\n", dw_readl(csi2, msk1)); + v4l2_info(sd, "MSK2: 0x%x\n", dw_readl(csi2, msk2)); + v4l2_info(sd, "PHY_TST_CTRL0: 0x%x\n", dw_readl(csi2, phy_tst_ctrl0)); + v4l2_info(sd, "PHY_TST_CTRL1: 0x%x\n", dw_readl(csi2, phy_tst_ctrl1)); return 0; } @@ -719,7 +746,7 @@ static int csi2_probe(struct platform_device *pdev) return -ENOMEM; csi2->dev = &pdev->dev; - + csi2->regs = &dw_csi2_v0; v4l2_subdev_init(&csi2->sd, &csi2_subdev_ops); v4l2_set_subdevdata(&csi2->sd, &pdev->dev); csi2->sd.internal_ops = &csi2_internal_ops; @@ -776,7 +803,7 @@ static void csi2_remove(struct platform_device *pdev) } static const struct of_device_id csi2_dt_ids[] = { - { .compatible = "fsl,imx6-mipi-csi2", }, + { .compatible = "fsl,imx6-mipi-csi2"}, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, csi2_dt_ids); -- 2.34.1