From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Frank Li <Frank.li@nxp.com>
Cc: linux-media@vger.kernel.org, Rui Miguel Silva <rmfrfs@gmail.com>,
Martin Kepplinger <martink@posteo.de>,
Purism Kernel Team <kernel@puri.sm>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
imx@lists.linux.dev, Stefan Klug <stefan.klug@ideasonboard.com>,
Sakari Ailus <sakari.ailus@iki.fi>
Subject: Re: [PATCH v1 1/6] media: imx-mipi-csis: Add VC-related register fields
Date: Fri, 7 Nov 2025 20:44:29 +0200 [thread overview]
Message-ID: <20251107184429.GF5558@pendragon.ideasonboard.com> (raw)
In-Reply-To: <aQ4cKf3y1zqwBmar@lizhi-Precision-Tower-5810>
On Fri, Nov 07, 2025 at 11:19:53AM -0500, Frank Li wrote:
> On Fri, Nov 07, 2025 at 03:58:08AM +0200, Laurent Pinchart wrote:
> > The CMN_CTRL and ISPCFG registers have fiels related to virtual channel
> > handling. In CMN_CTRL, the INTERLEAVE_MODE field is 2 bits wide, and
> > controls filtering by DT, VC or both. The VC number is then set in the
> > ISPCFG.VIRTUAL_CHANNEL field.
> >
> > Expand the definition of the register macros to support those features,
> > and set the VC ID to 0 explicitly instead of relying on the default
> > register value. This prepares for VC filtering but does not modify the
> > driver's behaviour.
> >
> > While at it, use GENMASK in the last few register mask macros that don't
> > use it.
> >
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> > drivers/media/platform/nxp/imx-mipi-csis.c | 19 ++++++++++++++++---
> > 1 file changed, 16 insertions(+), 3 deletions(-)
> >
> ...
> >
> > val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
> > - val &= ~MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK;
> > + val &= ~(MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK |
> > + MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_MASK);
> > +
> > val |= MIPI_CSIS_CMN_CTRL_LANE_NUMBER(lanes - 1);
> > +
> > if (csis->info->version == MIPI_CSIS_V3_3)
> > val |= MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT;
> > +
>
> above two empty line is not related this patch
It's just a matter of giving the code more room to breathe. I can move
them to patch 6/6 if you prefer.
> > mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
> >
> > __mipi_csis_set_format(csis, format, csis_fmt);
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2025-11-07 18:44 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-07 1:58 [PATCH v1 0/6] media: imx-mipi-csis: Add streams support Laurent Pinchart
2025-11-07 1:58 ` [PATCH v1 1/6] media: imx-mipi-csis: Add VC-related register fields Laurent Pinchart
2025-11-07 16:19 ` Frank Li
2025-11-07 18:44 ` Laurent Pinchart [this message]
2025-11-07 20:37 ` Frank Li
2025-11-07 1:58 ` [PATCH v1 2/6] media: imx-mipi-csis: Switch to .enable_streams() Laurent Pinchart
2025-11-07 16:29 ` Frank Li
2025-11-07 18:32 ` Laurent Pinchart
2025-11-07 1:58 ` [PATCH v1 3/6] media: imx-mipi-csis: Implement the .set_routing() operation Laurent Pinchart
2025-11-07 16:36 ` Frank Li
2025-11-07 18:30 ` Laurent Pinchart
2025-11-07 20:38 ` Frank Li
2025-11-09 21:48 ` kernel test robot
2025-11-07 1:58 ` [PATCH v1 4/6] media: imx-mipi-csis: Group runtime parameters in structure Laurent Pinchart
2025-11-07 16:40 ` Frank Li
2025-11-07 1:58 ` [PATCH v1 5/6] media: imx-mipi-csis: Set all per-channel registers in one function Laurent Pinchart
2025-11-07 16:37 ` Frank Li
2025-11-07 1:58 ` [PATCH v1 6/6] media: imx-mipi-csis: Add multi-channel support Laurent Pinchart
2025-11-07 16:48 ` Frank Li
2025-11-07 18:43 ` Laurent Pinchart
2025-11-20 3:12 ` G.N. Zhou
2025-11-20 15:23 ` Frank Li
2025-11-20 16:22 ` Laurent Pinchart
2025-12-02 0:59 ` [EXT] " G.N. Zhou
2025-11-07 9:31 ` [PATCH v1 0/6] media: imx-mipi-csis: Add streams support Martin Kepplinger
2025-11-07 18:28 ` Laurent Pinchart
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