From: Haibo Chen <haibo.chen@nxp.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
Haibo Chen <haibo.chen@nxp.com>,
imx@lists.linux.dev
Subject: [PATCH 3/4] mtd: spi-nor: micron-st: add mt35xu01gbba support
Date: Mon, 10 Nov 2025 12:02:58 +0800 [thread overview]
Message-ID: <20251110-nor-v1-3-cde50c81db05@nxp.com> (raw)
In-Reply-To: <20251110-nor-v1-0-cde50c81db05@nxp.com>
mt35xu01gbba is similar with mt35xu512aba, but with two dies.
SFDP contain the wrong size, so define the size dierctly in
the flash info. And it also support 8D-8D-8D mode, but SFDP
lack SNOR_F_IO_MODE_EN_VOLATILE, so add this fixup flags here.
Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
1) This mt35xu01gbba is populated on the imx95-19x19-evk board, was
tested at 200MHz using nxp,imx95-fspi SPI controller.
2) root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/partname
mt35xu01gbba
root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/jedec_id
2c5b1b
root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/manufacturer
micron
root@imx95evk:~# hexdump -Cv /sys/bus/spi/devices/spi1.0/spi-nor/sfdp
00000000 53 46 44 50 0a 01 03 ff 00 08 01 17 30 00 00 ff |SFDP........0...|
00000010 84 00 01 02 90 00 00 ff 05 01 01 06 a0 00 00 ff |................|
00000020 0a 00 01 08 b0 00 00 ff ff ff ff ff ff ff ff ff |................|
00000030 e5 20 8a ff ff ff ff 3f 00 00 00 00 00 00 00 00 |. .....?........|
00000040 ee ff ff ff ff ff 00 00 ff ff 00 00 0c 20 11 d8 |............. ..|
00000050 0f 52 00 00 39 61 99 00 87 8e 03 d3 ac a1 27 3d |.R..9a........'=|
00000060 7a 75 7a 75 fb bd d5 5c 00 00 70 ff 81 50 f8 a1 |zuzu...\..p..P..|
00000070 2f cb 27 8b 00 00 04 01 00 06 01 00 ff ff ff 8e |/.'.............|
00000080 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff ff |................|
00000090 43 0e ff ff 21 dc 5c ff ff ff ff ff ff ff ff ff |C...!.\.........|
000000a0 00 0b 80 9e b1 81 b5 85 00 f0 ff 9f 00 0a 00 00 |................|
000000b0 00 0a 1a 88 10 00 00 00 ff ff ff ff ff ff ff ff |................|
000000c0 00 00 06 01 00 00 00 00 14 01 81 03 00 00 00 00 |................|
000000d0
root@imx95evk:~# sha256sum /sys/bus/spi/devices/spi1.0/spi-nor/sfdp
3848f0bd2436d7ca1373cee33f90e09d6479d0f4dc4bfd19f6a082d9e0039495 /sys/bus/spi/devices/spi1.0/spi-nor/sfdp
3) root@imx95evk:~# cat /sys/kernel/debug/spi-nor/spi1.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-8S
opcode 0x7c
mode cycles 1
dummy cycles 7
1S-8S-8S
opcode 0xcc
mode cycles 1
dummy cycles 15
8D-8D-8D
opcode 0xfd
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
root@imx95evk:~# cat /sys/kernel/debug/spi-nor/spi1.0/params
name mt35xu01gbba
id 2c 5b 1b 10 41 00
size 128 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_LOCK | IO_MODE_EN_VOLATILE | SOFT_RESET
opcodes
read 0xfd
dummy cycles 20
erase 0xdc
program 0x12
8D extension repeat
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [1]
5c (32.0 KiB) [2]
dc (128 KiB) [3]
c4 (128 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+----------
00000000-07ffffff | [ 3] | no
4) root@imx95evk:~# dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.1 MB, 2.0 MiB) copied, 0.0207974 s, 101 MB/s
root@imx95evk:~# mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
root@imx95evk:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
root@imx95evk:~# hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
root@imx95evk:~# sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
root@imx95evk:~# mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
root@imx95evk:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
root@imx95evk:~# sha256sum spi*
57300768c1271d4588b850dcbf4e1400f287f09b2d515eda610890456695b205 spi_read
57300768c1271d4588b850dcbf4e1400f287f09b2d515eda610890456695b205 spi_test
root@imx95evk:~# mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
root@imx95evk:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
root@imx95evk:~# sha256sum spi*
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
57300768c1271d4588b850dcbf4e1400f287f09b2d515eda610890456695b205 spi_test
root@imx95evk:~# mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 134217728 (128M)
mtd.erasesize = 131072 (128K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
root@imx95evk:~# flash_erase /dev/mtd0 0 0
Erasing 131072 Kibyte @ 0 -- 100 % complete
root@imx95evk:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
root@imx95evk:~# hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
---
drivers/mtd/spi-nor/micron-st.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 89cd146095584ddebdd258a186f6398b420e5800..f724313f4dd3720908968c670e8d3d58f41c099c 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -208,6 +208,12 @@ static const struct spi_nor_fixups mt35xu512aba_fixups = {
.late_init = micron_st_nor_one_die_late_init,
};
+static const struct spi_nor_fixups mt35xu01gbba_fixups = {
+ .default_init = mt35xu512aba_default_init,
+ .post_sfdp = mt35xu512aba_post_sfdp_fixup,
+ .late_init = micron_st_nor_two_die_late_init,
+};
+
static const struct flash_info micron_nor_parts[] = {
{
.id = SNOR_ID(0x2c, 0x5b, 0x1a),
@@ -219,6 +225,16 @@ static const struct flash_info micron_nor_parts[] = {
.mfr_flags = USE_FSR,
.fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
.fixups = &mt35xu512aba_fixups,
+ }, {
+ .id = SNOR_ID(0x2c, 0x5b, 0x1b),
+ .name = "mt35xu01gbba",
+ .sector_size = SZ_128K,
+ .size = SZ_128M,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ |
+ SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP,
+ .mfr_flags = USE_FSR,
+ .fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
+ .fixups = &mt35xu01gbba_fixups,
}, {
.id = SNOR_ID(0x2c, 0x5b, 0x1c),
.name = "mt35xu02g",
--
2.34.1
next prev parent reply other threads:[~2025-11-10 4:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-10 4:02 [PATCH 0/4] mtd: spi-nor: micron-st: add die erase for micron spi nor chip Haibo Chen
2025-11-10 4:02 ` [PATCH 1/4] mtd: spi-nor: micron-st: rename the die_late_init functions Haibo Chen
2025-11-10 6:32 ` Tudor Ambarus
2025-11-10 4:02 ` [PATCH 2/4] mtd: spi-nor: micron-st: add die erase for mt35xu512aba Haibo Chen
2025-11-10 6:38 ` Tudor Ambarus
2025-11-11 7:36 ` Bough Chen
2025-11-10 4:02 ` Haibo Chen [this message]
2025-11-10 6:42 ` [PATCH 3/4] mtd: spi-nor: micron-st: add mt35xu01gbba support Tudor Ambarus
2025-11-11 7:54 ` Bough Chen
2025-11-11 8:23 ` Tudor Ambarus
2025-11-10 4:02 ` [PATCH 4/4] mtd: spi-nor: micron-st: enable 8D-8D-8D mode and die erase for mt35xu02gcba Haibo Chen
2025-11-10 6:45 ` Tudor Ambarus
2025-11-11 8:00 ` Bough Chen
2025-11-11 8:29 ` Tudor Ambarus
2025-11-11 8:33 ` Bough Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251110-nor-v1-3-cde50c81db05@nxp.com \
--to=haibo.chen@nxp.com \
--cc=imx@lists.linux.dev \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=miquel.raynal@bootlin.com \
--cc=mwalle@kernel.org \
--cc=pratyush@kernel.org \
--cc=richard@nod.at \
--cc=tudor.ambarus@linaro.org \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).