[PATCH v4 0/3] Fix concurrency issues between G1 and G2 on

[ming.qian@oss.nxp.com]

From: Ming Qian <ming.qian@oss.nxp.com>

On the i.MX8MQ, we encountered some concurrency issues with H264 and HEVC
decoding.

There are two main reasons:
1. The vpu blk-ctrl don't have separate reset and clock enable bits.
2. The g1 VPU and g2 VPU cannot decode simultaneously.

We attempted to make corresponding fix to address these two issues.

Ming Qian (2):
  pmdomain: imx8m-blk-ctrl: Remove separate rst and clk mask for 8mq vpu
  media: verisilicon: Avoid G2 bus error while decoding H.264 and HEVC

Nicolas Dufresne (1):
  media: v4l2-mem2mem: Add a kref to the v4l2_m2m_dev structure

 drivers/media/platform/verisilicon/hantro.h   |  2 +
 .../media/platform/verisilicon/hantro_drv.c   | 42 +++++++++++++++++--
 .../media/platform/verisilicon/imx8m_vpu_hw.c |  8 ++++
 drivers/media/v4l2-core/v4l2-mem2mem.c        | 23 ++++++++++
 drivers/pmdomain/imx/imx8m-blk-ctrl.c         | 11 +++--
 include/media/v4l2-mem2mem.h                  | 21 ++++++++++
 6 files changed, 100 insertions(+), 7 deletions(-)

-- 
2.52.0