From: Eduard Bostina <egbostina@gmail.com>
To: daniel.baluta@nxp.com, simona.toaca@nxp.com, egbostina@gmail.com,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [RFC PATCH] arm64: dts: imx8mp-edm-g-wb: Use 0 for reserved bit
Date: Tue, 10 Mar 2026 09:10:53 +0000 [thread overview]
Message-ID: <20260310091054.2029912-1-egbostina@gmail.com> (raw)
The i.MX8MP Reference Manual documents bit 0 of the
IOMUXC_SW_PAD_CTL_PAD registers as reserved. The hd3ss3220
IRQ pin (SAI1_RXD6/GPIO4_IO08) currently uses pad config
value 0x41 which sets this reserved bit.
Change 0x41 to 0x40 to leave the reserved bit cleared, as
recommended by the reference manual. This also allows for
easier conversion to symbolic macros.
Signed-off-by: Eduard Bostina <egbostina@gmail.com>
---
arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts
index 242fa930b..a78401d11 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts
@@ -345,7 +345,7 @@ MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x16 /* DSI_VDDEN */
pinctrl_hd3ss3220_irq: hd3ss3220-irqgrp {
fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x41 /* GPIO_P253 */
+ MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40 /* GPIO_P253 */
>;
};
--
2.43.0
next reply other threads:[~2026-03-10 9:11 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-10 9:10 Eduard Bostina [this message]
2026-03-24 15:47 ` [RFC PATCH] arm64: dts: imx8mp-edm-g-wb: Use 0 for reserved bit Frank Li
2026-03-25 9:50 ` Eddie
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