Re: [PATCH 3/5] mailbox: imx: Move the RXDB part of the mailbox into the threaded handler

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect bitmask macro used when unmasking RXDB interrupts in the threaded IRQ handler.
--

commit 52f5529242040f4be31a0457d8d67afe5b6d8073
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

mailbox: imx: Move the RXDB part of the mailbox into the threaded handler

This commit moves the RXDB callback handling into the threaded handler for
the i.MX mailbox driver. It unconditionally unmasks the RXDB interrupt in
the threaded handler after processing, similar to how the standard RX
interrupts are handled.

> diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
> --- a/drivers/mailbox/imx-mailbox.c
> +++ b/drivers/mailbox/imx-mailbox.c
[ ... ]
> @@ -528,6 +528,12 @@ static irqreturn_t imx_mu_isr_th(int irq, void *p)
>  			imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
>  		return IRQ_HANDLED;
>  
> +	case IMX_MU_TYPE_RXDB:
> +		cp->pending = 0;
> +		priv->dcfg->rxdb(priv, cp);
> +		imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);

[Severity: High]
Does this code use the correct bitmask macro for unmasking the RXDB interrupt?

The IMX_MU_TYPE_RXDB case appears to be using IMX_MU_xCR_RIEn (Receive
Interrupt Enable) instead of IMX_MU_xCR_GIEn (General Purpose Interrupt
Enable) to generate the bitmask.

On non-V2 hardware, these macros target different bit ranges (bits 24-27 for
RIEn vs bits 28-31 for GIEn). Could this leave the RXDB interrupt permanently
masked after it fires once, and inadvertently set incorrect bits in the
control register?

> +		return IRQ_HANDLED;
> +
>  	default:

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260529-imx_mbox_rproc-v1-0-b8ffc36e11e5@linutronix.de?part=3