From: sashiko-bot@kernel.org
To: hongxing.zhu@oss.nxp.com
Cc: linux-pci@vger.kernel.org, Frank.Li@kernel.org, imx@lists.linux.dev
Subject: Re: [PATCH v2] PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability
Date: Wed, 08 Jul 2026 04:10:52 +0000 [thread overview]
Message-ID: <20260708041053.5F39C1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260708035928.580236-3-hongxing.zhu@oss.nxp.com>
> From: Richard Zhu <hongxing.zhu@nxp.com>
>
> Bandwidth marginality was observed during i.MX95 Gen3 PCIe tests with
> the default MPLLB_BINDWIDTH value. This margin degradation worsens
> across voltage and temperature (VT) variations and different test
> matrices, potentially causing link stability issues.
>
> Testing with MPLLB_BINDWIDTH value of 140 (0x8c) shows significant
> improvement in bandwidth margins across all VT conditions and test
> scenarios.
>
> Implement PHY register write helper function and configure:
> - MPLLB_BW_OVRD_IN = 140 (0x8c) for improved bandwidth margin
> - MPLLB_BW_OVRD_EN to enable the override
>
> This ensures robust PCIe Gen3 performance across all operating
> conditions.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260708035928.580236-3-hongxing.zhu@oss.nxp.com?part=1
next prev parent reply other threads:[~2026-07-08 4:10 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-08 3:59 [PATCH v2] PCI: imx6: Add runtime PM support for i.MX95 hongxing.zhu
2026-07-08 3:59 ` [PATCH v2] PCI: imx6: Fix i.MX6Q/DL boot hang by separating PHY power and reference clock control hongxing.zhu
2026-07-08 4:06 ` sashiko-bot
2026-07-08 15:28 ` Frank Li
2026-07-08 3:59 ` [PATCH v2] PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability hongxing.zhu
2026-07-08 4:10 ` sashiko-bot [this message]
2026-07-08 15:19 ` Frank Li
2026-07-09 7:55 ` Hongxing Zhu (OSS)
2026-07-09 15:08 ` Frank Li
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