From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69700403135 for ; Tue, 25 Aug 2026 12:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787659876; cv=none; b=SGRHxQsSmUSMhW4jC+xUMgywUtC0VgWjDf0Fp2HrE43hBhe4JqIapICKiw677NEd8VatLlgKVmV/sLB83CbS9VYucLF8g1awnWPIk1UCRGFm/4bjmQQvhg1Jb8f3Pedd8xqABgpIb7AKBWQszjqeDiGg46dKwZTYuKlrxYnZDXM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787659876; c=relaxed/simple; bh=VXvb7zk6e679p4fGHbBW0TMSen0aQsbibwXJQXvTmtg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lLdOYFO2w1ntKnDZjzv9tr7tew1rQZiP1YBwhbMy0PROx7ktq0hWFlBqQQ1tq5sx2lPKikT6MpnOuS+TyFuwzLXrCJw+zxrzLJDK0recarghXPyrPu96RqGBZo7fKTyGBhpEo1u2o0H/dCGBitR6ZvMIkMawKw2a3w4D8KAncK0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=tFg7uNlL; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="tFg7uNlL" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-6a422090b14so6257928a12.1 for ; Tue, 25 Aug 2026 05:11:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787659872; x=1788264672; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=3m/EDZr4T39sfvz1Va34weL4DM8C2AwTVI2AUMgcU1g=; b=tFg7uNlLXPQNc7rViRUO6Xann4cuL12HXgO5mhlsv820sCbVpwYrPGo1tbc1eGJWoE cZzx+DUrs6UW/W67buwf26FAqabtFfgxYwPy5Ud/uZDTwIRAYCcdp73IaVQ3WsPZeQaB bm3ZU2vsP01UfnmicDRAE3EK2otfQLYLzaxEnTcAR+UeWTWKQMlkRXwiTgmlp6eOW8sx MfSCMiiXtO7W2eCmJCZojhZGX9Bo+yCQwtR5DM7TmdYBta6o9EfrHUArI4LYu2fayeUM D1Rg/lIF+sYvccd8MteGdaYyOXdXaOiofk1MdR8TlBe2285sNTwvHM0dKndm6szIjyyS 7vsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787659872; x=1788264672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=3m/EDZr4T39sfvz1Va34weL4DM8C2AwTVI2AUMgcU1g=; b=XXhre8T3JemnnrsGwTVVKAOQhdBVMTTXqw2rGbqNkXNmVqie/RlhxQLq4+t6kAZm7R qnl3CsNcAoL/rwGUKaRwCArsbUZv6IFIqFuaXXhfNMZOSh67+NUgb9Do7ZHfCbYSROYE 8gnM54xklBWTCRE5asS9eaEIhRRUnrrNkqwszWisgWapZ3jAZfktaTBhgvuypKa/Lt21 7f4Nv6jAAnElcpceezqTAWLgmpXbQCkK4muY89AwrdHZMu1UDtoVQ8fovFVSedJhhlYo 4qExUXACV8hIsbtuTHddi9BP2i9tQ2xq9otuHy4AB2s0d6/VOanXIS/7WcEMZWEIJ0lA iTgg== X-Forwarded-Encrypted: i=1; AHgh+RqXTQPJhB6FLQp51GUSF9eQn9k0KGd+2W9D9pRK/jlOhrdH50ckPEtyXJUS0HLFy2vuBzA=@lists.linux.dev X-Gm-Message-State: AFuF++lzZkKiJbhc3SUGCnkhba7Px1dyBo9b7zAnOSkydOlPABjdiZYF jZHlx434jLFbqfl4wj3EHootToVaM629WdOlePtuOx1jo36PnVVOti4I X-Gm-Gg: AR+sD11pj/DPBU0p4FhtfHnutGD+lDoTTgQ0mUZPCep+IdOqBOeXTzNMDhJC/kpNbcO I8ubFXcmV21mzq4uuAzFMAgREOp8xSCLYjpshNYR4Ti3PDZiIeXlHapPvea2bs2gI0LbcEJJrZG q9uKAf9WykgmHRIbh5ZKUJ1xlVeg2YhS1ccPZepssota4gFvenvJ1nnoUJ6rsTMIlI9SihHYgf+ c73yckoiN4i0UEHHnq7ESmWWnanWsnq8Q/tE+KuYUMRty0RDD7cAQLXpoVj1OUYQjdR5TRmR6Cw M1xCtdiOmpuiDinRE5H6+4K8G29nj7d822D6f7n7rI1fD4cPX6B8KF8RkX7Q8zpgwRXHyXq2nvl rXc/Co/M6KzD0y5VilZ6coPv7w0bm1U8iKOO1NbnkJzhCptMpRFp2kP8+EoMworkQwy0sQFi/E5 dNyz9O9kBjov8j3xJj0w7GnTZoL333SYxElzFtBlmVHlw5DSfnszo7iQ7AuiHi9hrpRgl8Q3OuB OZ6DvKPitOhP8I= X-Received: by 2002:a05:6402:20cd:b0:6a3:6d83:ba44 with SMTP id 4fb4d7f45d1cf-6a582b05701mr30688214a12.2.1787659872446; Tue, 25 Aug 2026 05:11:12 -0700 (PDT) Received: from SMW024614.wbi.nxp.com ([128.77.115.158]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a59e199767sm13841351a12.15.2026.08.25.05.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2026 05:11:11 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Fabio Estevam , elena.popa@nxp.com, cosmin.stoica@nxp.com Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] arm64: dts: freescale: add MR-NAVQ95 basic board support Date: Tue, 25 Aug 2026 05:08:12 -0700 Message-ID: <20260825120812.2152-3-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260825120812.2152-1-laurentiumihalcea111@gmail.com> References: <20260825120812.2152-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Laurentiu Mihalcea Add basic support for NXP's MR-NAVQ95 board. This board is designed for robotics applications (e.g. drones, rovers, humanoids, etc..) and has the following hardware feats (list is not exhaustive): * based on i.MX95 19x19 SoC * 64GB eMMC * up to 16GB of LPDDR5 memory * 1 x USB 2.0 TypeC * 1 x USB 3.0 TypeC * 1 x RJ45 port with RTL8211 PHY The support targets revision B of the board. Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx95-navq.dts | 267 +++++++++++++++++++ 2 files changed, 268 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-navq.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 95ae85ab4adf..4c5ef83cd857 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -712,6 +712,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-frdm-pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-clover.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-navq.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596la-mba95xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-navq.dts b/arch/arm64/boot/dts/freescale/imx95-navq.dts new file mode 100644 index 000000000000..f7ddc39f9b21 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-navq.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; + +#include "imx95.dtsi" + +/ { + model = "NXP MR-NAVQ95"; + compatible = "fsl,imx95-navq", "fsl,imx95"; + + aliases { + ethernet0 = &enetc_port0; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <12000>; + }; +}; + +&edma1 { + /* owned by M7 */ + status = "reserved"; +}; + +&edma2 { + /* channels 30-63 owned by M7 */ + dma-channels = <30>; +}; + +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&lpi2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + clock-frequency = <400000>; + status = "okay"; + + i2c3_gpio_expander_21: gpio-expander@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_gpio_expander_21>; + }; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + status = "okay"; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + reset-gpios = <&i2c3_gpio_expander_21 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,clkout-disable; + }; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_i2c3_gpio_expander_21: i2c3gpioexpander21grp { + fsl,pins = < + IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; -- 2.53.0