From: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>
To: Marc Kleine-Budde <mkl@pengutronix.de>,
Vincent Mailhol <mailhol@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Angelo Dureghello <angelo@kernel-space.org>,
Frank Li <Frank.Li@nxp.com>
Cc: linux-can@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, NXP S32 Linux Team <s32@nxp.com>,
imx@lists.linux.dev, Christophe Lizzi <clizzi@redhat.com>,
Alberto Ruiz <aruizrui@redhat.com>,
Enric Balletbo <eballetb@redhat.com>,
Eric Chanudet <echanude@redhat.com>,
Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>,
Haibo Chen <haibo.chen@nxp.com>
Subject: [PATCH v7 2/6] can: flexcan: disable all IRQ lines in flexcan_chip_interrupts_enable()
Date: Mon, 31 Aug 2026 16:34:45 +0200 [thread overview]
Message-ID: <20260831143449.12828-3-ciprianmarian.costea@oss.nxp.com> (raw)
In-Reply-To: <20260831143449.12828-1-ciprianmarian.costea@oss.nxp.com>
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
flexcan_chip_interrupts_enable() disables only the primary IRQ line while
writing to the IMASK and CTRL registers.
On multi-IRQ platforms (S32G2, MCF5441X), the additional IRQ lines (boff,
err, secondary-mb) remain active so their handlers can fire while
registers are inconsistent.
Disable all registered IRQ lines around the IMASK/CTRL writes. This
also fixes the resume path, which calls this function.
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Vincent Mailhol <mailhol@kernel.org>
Reviewed-and-tested-by: Haibo Chen <haibo.chen@nxp.com>
Tested-by: Enric Balletbo i Serra <eballetb@redhat.com>
---
drivers/net/can/flexcan/flexcan-core.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c
index 2e9df2d14b34..4eda54d2169e 100644
--- a/drivers/net/can/flexcan/flexcan-core.c
+++ b/drivers/net/can/flexcan/flexcan-core.c
@@ -1522,14 +1522,28 @@ static void flexcan_chip_interrupts_enable(const struct net_device *dev)
{
const struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->regs;
+ u32 quirks = priv->devtype_data.quirks;
u64 reg_imask;
disable_irq(dev->irq);
+ if (quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
+ disable_irq(priv->irq_boff);
+ disable_irq(priv->irq_err);
+ }
+ if (quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ)
+ disable_irq(priv->irq_secondary_mb);
+
priv->write(priv->reg_ctrl_default, ®s->ctrl);
reg_imask = priv->rx_mask | priv->tx_mask;
priv->write(upper_32_bits(reg_imask), ®s->imask2);
priv->write(lower_32_bits(reg_imask), ®s->imask1);
enable_irq(dev->irq);
+ if (quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ)
+ enable_irq(priv->irq_secondary_mb);
+ if (quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
+ enable_irq(priv->irq_boff);
+ enable_irq(priv->irq_err);
+ }
}
static void flexcan_chip_interrupts_disable(const struct net_device *dev)
--
2.43.0
next prev parent reply other threads:[~2026-08-31 14:35 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-31 14:34 [PATCH v7 0/6] can: flexcan: Add NXP S32N79 SoC support Ciprian Costea
2026-08-31 14:34 ` [PATCH v7 1/6] can: flexcan: use dedicated IRQ handlers for multi-IRQ platforms Ciprian Costea
2026-08-31 18:01 ` sashiko-bot
2026-09-01 14:44 ` Ciprian Marian Costea
2026-08-31 14:34 ` Ciprian Costea [this message]
2026-08-31 18:15 ` [PATCH v7 2/6] can: flexcan: disable all IRQ lines in flexcan_chip_interrupts_enable() sashiko-bot
2026-08-31 14:34 ` [PATCH v7 3/6] can: flexcan: split rx/tx masks per mailbox IRQ line Ciprian Costea
2026-08-31 18:27 ` sashiko-bot
2026-08-31 14:34 ` [PATCH v7 4/6] dt-bindings: can: fsl,flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-08-31 18:37 ` sashiko-bot
2026-08-31 14:34 ` [PATCH v7 5/6] can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk Ciprian Costea
2026-08-31 18:51 ` sashiko-bot
2026-08-31 14:34 ` [PATCH v7 6/6] can: flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-08-31 19:01 ` sashiko-bot
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