Re: [PATCH v2 08/10] arm64: dts: freescale: s32n79: Add UFS host controller

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing Clock Enable for the UFS Core Clock
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commit 90b92b70b82e1240cda14e91539c0096398b8f62
Author: Larisa Grigore <larisa.grigore@oss.nxp.com>

arm64: dts: freescale: s32n79: Add UFS host controller

Add the S32N79 UFS host controller node to the SoC dtsi. The controller
remains disabled by default and is enabled by board dts files as needed.

> diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi
> index 94ab58783fdc8..0b51ca8bc7f9b 100644
> --- a/arch/arm64/boot/dts/freescale/s32n79.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi
> @@ -100,6 +100,16 @@ uart7: serial@4aa40000 {
>  			status = "disabled";
>  		};
>  
> +		ufshc: ufs@4ac80000 {
> +			compatible = "nxp,s32n79-ufshc", "jedec,ufs-2.0";
> +			reg = <0x4ac80000 0x1000>, <0x4ac40000 0x1000>;
> +			reg-names = "ufshc", "scm";
> +			interrupt-parent = <&irqsteer_coss>;
> +			interrupts = <211>;
> +			clocks = <&clks 0x92>;

[Severity: High]
Does this node need a clock-names property to ensure the clock is enabled?

Without clock-names, the UFS core framework's automatic clock management
(ufshcd_setup_clocks) is bypassed. The ufs-nxp-s32n7 driver fetches this
clock via devm_clk_get() in ufs_s32n_init():

	ufs->core_clk = devm_clk_get(dev, NULL);
	if (IS_ERR(ufs->core_clk))
		return dev_err_probe(dev, PTR_ERR(ufs->core_clk),
				     "Failed to get core clock.\n");

However, the driver never calls clk_prepare_enable(). Additionally, without a
power-domains property, the generic PM domain framework will not implicitly
enable the clock.

Could this cause the Common Clock Framework to disable it as an unused clock
during late initialization, leading to a bus lockup or synchronous external
abort when the device's memory-mapped registers are accessed?

> +			status = "disabled";
> +		};
> +
>  		irqsteer_coss: interrupt-controller@4ed00000 {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260914125000.30812-1-larisa.grigore@oss.nxp.com?part=8