Re: [net-next,PATCH v1] enetc: Increase eMDIO MDC rate to 1.2 MHz

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] enetc: MDIO clock overclocked beyond 2.5MHz on 400MHz platforms
- [Medium] enetc: incorrect MDIO divisor math for target 1.2MHz clock
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commit ef3369dd3505cf8547f6092963680d7b7aec54e6
Author: Marek Vasut <marex@nabladev.com>

enetc: Increase eMDIO MDC rate to 1.2 MHz

This commit attempts to increase the eMDIO MDC clock rate to 1.2 MHz to
support PHYs that require at least a 1 MHz MDC clock, such as the NXP TJA1120.
It does this by modifying the globally hardcoded MDIO_CFG_CLKDIV value from
258 to 138.

> diff --git a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
> index 998aaa394e9c4..30ea91cea00e5 100644
> --- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
> +++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
> @@ -24,7 +24,7 @@
>  
>  #define ENETC_EMDIO_CFG \
>  	(MDIO_CFG_HOLD(2) | \
> -	 MDIO_CFG_CLKDIV(258) | \
> +	 MDIO_CFG_CLKDIV(138) | \

[Severity: High]
Does this hardcoded divisor result in overclocking the MDIO bus beyond the
2.5 MHz IEEE 802.3 specification limit on platforms with higher base clock
frequencies?

For instance, on platforms like LS1028A where the ENETC system clock is 400
MHz (ENETC_CLK_400M), a divisor of 138 yields an MDC frequency of roughly
2.898 MHz (400 MHz / 138). Could this overclocking cause communication
failures or silent data corruption with standard 2.5 MHz PHYs?

[Severity: Medium]
Does this new divisor mathematically produce the 1.2 MHz clock rate claimed
by the patch?

The commit message states that the old divisor of 258 yields a 558 kHz MDC
rate on i.MX95, implying a base clock of ~144 MHz (558 kHz * 258). With a
~144 MHz base clock, a divisor of 138 yields an MDC rate of ~1.043 MHz
(144 MHz / 138), not 1.2 MHz.

To achieve the 1.2 MHz clock claimed in the commit, should the divisor be
set to 120 (144 MHz / 1.2 MHz = 120)? While 1.043 MHz satisfies the >= 1 MHz
requirement for the TJA1120 PHY, it appears to be a mismatch with the commit
message's stated target.

>  	 MDIO_CFG_NEG)
>  
>  #define MDIO_CTL_DEV_ADDR(x)	((x) & 0x1f)

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Sashiko AI review · https://sashiko.dev/#/patchset/20260924003132.580306-1-marex@nabladev.com?part=1