Re: [net-next,PATCH v2] enetc: Increase eMDIO MDC rate to 2.5 MHz

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] enetc: hardcoded MDIO clock divider change overclocks MDC on faster platforms
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commit f8edf987f57daf3802702cc91c7af187a4c08ef1
Author: Marek Vasut <marex@nabladev.com>

enetc: Increase eMDIO MDC rate to 2.5 MHz

This commit lowers the global MDIO clock divider from 258 to 66 to increase
the MDC rate to 2.5 MHz for the i.MX95 B0 platform.

> diff --git a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
> index 998aaa394e9c4..a90a04a47befd 100644
> --- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
> +++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
> @@ -24,7 +24,7 @@
>  
>  #define ENETC_EMDIO_CFG \
>  	(MDIO_CFG_HOLD(2) | \
> -	 MDIO_CFG_CLKDIV(258) | \
> +	 MDIO_CFG_CLKDIV(66) | \
         ^^^^^^^^^^^^^^^^^^^^

[Severity: High]
Does hardcoding this lower divider overclock the MDC frequency on platforms
with a faster base clock?

The enetc_mdio.c driver is also used on other platforms like the LS1028A,
which typically run the ENETC system clock at a much faster rate (e.g.,
333 - 400 MHz).

Applying a divider of 66 on a 400 MHz clock yields an MDC frequency of
~6.06 MHz. This exceeds the IEEE 802.3 Clause 22 maximum MDC frequency of
2.5 MHz (400 ns minimum period).

Will this break MDIO communication with PHYs on these existing boards?
Should the driver dynamically calculate the divider based on the platform's
actual clock rate rather than hardcoding a value tailored only for the
i.MX95?

>  	 MDIO_CFG_NEG)
>  
>  #define MDIO_CTL_DEV_ADDR(x)	((x) & 0x1f)

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Sashiko AI review · https://sashiko.dev/#/patchset/20260924180607.60932-1-marex@nabladev.com?part=1