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a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1749546082; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rnLI7TEbgPq4uvBO5xH2GP7XBad6KtOS6WYu+5UVOJ0=; b=EVMgaWV79PJusbQbTNgGwIDCOI7bvZmFxG8Zaj5vg7cxW1O0j00284tOZCJ8AtR7LXT0Po yLdoBz5u3ahQOX+O5GiaXtIRidZdVh5kTRJ9yJJlVrIjHTdDjVXMCXGpcCDIoCpOIiNYd0 mP9SfHZPYIxZXPZSLMKt2cHb6w9xDbFH/G9QHaZYSSLFvk9oJgIWs+f6cIjv9PmSAbWWtT qSwlw3HGCMjvWo+TJeTVRFmsxvUgGFuran1BJQGE/fOFAAgd4TAJ3XDp/zSYzcS5qkZquG rdYmpbTZp/BqXaUC7eCWydnNUrhzTuIzRPamdJA7EMUdt7nhxx4rX0M9Q96Ybg== From: Alexander Stein To: linux-media@vger.kernel.org, Laurent Pinchart Cc: Isaac Scott , Rui Miguel Silva , Martin Kepplinger , Purism Kernel Team , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 8/8] media: imx-mipi-csis: Initial support for multiple output channels Date: Tue, 10 Jun 2025 11:01:20 +0200 Message-ID: <2230307.irdbgypaU6@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20250608235840.23871-9-laurent.pinchart@ideasonboard.com> References: <20250608235840.23871-1-laurent.pinchart@ideasonboard.com> <20250608235840.23871-9-laurent.pinchart@ideasonboard.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" X-Last-TLS-Session-Version: TLSv1.3 Hi Laurent, thanks for the patch. Am Montag, 9. Juni 2025, 01:58:40 CEST schrieb Laurent Pinchart: > Some CSIS instances feature more than one output channel. Parse the > number of channels from the device tree, and update register dumps and > event counters accordingly. Support for routing virtual channels and > data types to output channels through the subdev internal routing API > will come later. >=20 > Signed-off-by: Laurent Pinchart > --- > drivers/media/platform/nxp/imx-mipi-csis.c | 224 ++++++++++++++------- > 1 file changed, 146 insertions(+), 78 deletions(-) >=20 > diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/p= latform/nxp/imx-mipi-csis.c > index 080e40837463..4cc358d93187 100644 > --- a/drivers/media/platform/nxp/imx-mipi-csis.c > +++ b/drivers/media/platform/nxp/imx-mipi-csis.c > @@ -98,12 +98,12 @@ > #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28) > #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28) > #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) As a side note: I just noticed Bits 28-31 are only defined on i.MX7. They are reserved on i.MX8M (Mini, Nano, Plus). > -#define MIPI_CSIS_INT_SRC_FRAME_START BIT(24) > -#define MIPI_CSIS_INT_SRC_FRAME_END BIT(20) > +#define MIPI_CSIS_INT_SRC_FRAME_START(n) BIT((n) + 24) > +#define MIPI_CSIS_INT_SRC_FRAME_END(n) BIT((n) + 20) > #define MIPI_CSIS_INT_SRC_ERR_SOT_HS(n) BIT((n) + 16) > -#define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12) > -#define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8) > -#define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4) > +#define MIPI_CSIS_INT_SRC_ERR_LOST_FS(n) BIT((n) + 12) > +#define MIPI_CSIS_INT_SRC_ERR_LOST_FE(n) BIT((n) + 8) > +#define MIPI_CSIS_INT_SRC_ERR_OVER(n) BIT((n) + 4) Similar here. Only i.MX7 has the bits for CH1, CH2 and CH3 defined. > #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) > #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) > #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1) > @@ -205,23 +205,23 @@ > /* Debug control register */ > #define MIPI_CSIS_DBG_CTRL 0xc0 > #define MIPI_CSIS_DBG_INTR_MSK 0xc4 > -#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25) > -#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24) > -#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20) > -#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16) > -#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12) > -#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8) > -#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4) > -#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0) > +#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25) > +#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24) > +#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE(n) BIT((n) + 20) > +#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME(n) BIT((n) + 16) > +#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE(n) BIT((n) + 12) > +#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS(n) BIT((n) + 8) > +#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL(n) BIT((n) + 4) > +#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE(n) BIT((n) + 0) > #define MIPI_CSIS_DBG_INTR_SRC 0xc8 > -#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25) > -#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24) > -#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20) > -#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16) > -#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12) > -#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8) > -#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4) > -#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0) > +#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25) > +#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24) > +#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(n) BIT((n) + 20) > +#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(n) BIT((n) + 16) > +#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(n) BIT((n) + 12) > +#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(n) BIT((n) + 8) > +#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(n) BIT((n) + 4) > +#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(n) BIT((n) + 0) Out of curiosity: Where do these bits come from? I can't find them in RM. Best regards, Alexander > [snip] =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/