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Thu, 30 Oct 2025 11:54:12 +0100 (CET) From: Alexander Stein To: frank.li@nxp.com, l.stach@pengutronix.de, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-arm-kernel@lists.infradead.org Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Zhu , Richard Zhu Subject: Re: [PATCH v6 10/11] PCI: imx6: Add CLKREQ# override to enable REFCLK for i.MX95 PCIe Date: Thu, 30 Oct 2025 11:54:11 +0100 Message-ID: <3022129.e9J7NaK4W3@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20251015030428.2980427-11-hongxing.zhu@nxp.com> References: <20251015030428.2980427-1-hongxing.zhu@nxp.com> <20251015030428.2980427-11-hongxing.zhu@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; 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Oktober 2025, 05:04:27 CET schrieb Richard Zhu: > The CLKREQ# is an open drain, active low signal that is driven low by > the card to request reference clock. It's an optional signal added in > PCIe CEM r4.0, sec 2. Thus, this signal wouldn't be driven low if it's > reserved. >=20 > On i.MX95 EVK board, the PCIe slot connected to the second PCIe > controller is one standard PCIe slot. The default voltage of CLKREQ# is > not active low, and may not be driven to active low due to the potential > scenario listed above (e.x INTEL e1000e network card). >=20 > Since the reference clock controlled by CLKREQ# is required by i.MX95 > PCIe host too. To make sure this clock is ready even when the CLKREQ# > isn't driven low by the card(e.x the scenario described above), force > CLKREQ# override active low for i.MX95 PCIe host to enable reference > clock. >=20 > Signed-off-by: Richard Zhu Thanks, this is actually required on TQMa95xxSA. Tested-by: Alexander Stein > --- > drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) >=20 > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controll= er/dwc/pci-imx6.c > index a60fe7c337e08..aa5a4900d0eb6 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -52,6 +52,8 @@ > #define IMX95_PCIE_REF_CLKEN BIT(23) > #define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9) > #define IMX95_PCIE_SS_RW_REG_1 0xf4 > +#define IMX95_PCIE_CLKREQ_OVERRIDE_EN BIT(8) > +#define IMX95_PCIE_CLKREQ_OVERRIDE_VAL BIT(9) > #define IMX95_PCIE_SYS_AUX_PWR_DET BIT(31) > =20 > #define IMX95_PE0_GEN_CTRL_1 0x1050 > @@ -711,6 +713,22 @@ static int imx7d_pcie_enable_ref_clk(struct imx_pcie= *imx_pcie, bool enable) > return 0; > } > =20 > +static void imx95_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool = enable) > +{ > + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1, > + IMX95_PCIE_CLKREQ_OVERRIDE_EN, > + enable ? IMX95_PCIE_CLKREQ_OVERRIDE_EN : 0); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1, > + IMX95_PCIE_CLKREQ_OVERRIDE_VAL, > + enable ? IMX95_PCIE_CLKREQ_OVERRIDE_VAL : 0); > +} > + > +static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool ena= ble) > +{ > + imx95_pcie_clkreq_override(imx_pcie, enable); > + return 0; > +} > + > static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) > { > struct dw_pcie *pci =3D imx_pcie->pci; > @@ -1918,6 +1936,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { > .core_reset =3D imx95_pcie_core_reset, > .init_phy =3D imx95_pcie_init_phy, > .wait_pll_lock =3D imx95_pcie_wait_for_phy_pll_lock, > + .enable_ref_clk =3D imx95_pcie_enable_ref_clk, > }, > [IMX8MQ_EP] =3D { > .variant =3D IMX8MQ_EP, > @@ -1974,6 +1993,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { > .core_reset =3D imx95_pcie_core_reset, > .wait_pll_lock =3D imx95_pcie_wait_for_phy_pll_lock, > .epc_features =3D &imx95_pcie_epc_features, > + .enable_ref_clk =3D imx95_pcie_enable_ref_clk, > .mode =3D DW_PCIE_EP_TYPE, > }, > }; >=20 =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/