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Thu, 12 Jun 2025 07:35:10 -0700 (PDT) Message-ID: <31a16580-e3ce-4cc8-8310-04a0dd292df5@linaro.org> Date: Thu, 12 Jun 2025 15:35:09 +0100 Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] spi: spi-fsl-dspi: Use non-coherent memory for DMA To: Vladimir Oltean Cc: Arnd Bergmann , Frank Li , Vladimir Oltean , Mark Brown , linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org References: <20250609-james-nxp-spi-dma-v1-2-2b831e714be2@linaro.org> <20250611090107.t35zatn47vetnvse@skbuf> <20250612111514.rfb3gpmlilznrfxs@skbuf> <20250612142306.3c3dl46z326xvcud@skbuf> <5b21c4c9-0ef7-41e5-a3bb-5a48a0c73644@linaro.org> <20250612143157.bu4vayvhieohdtbu@skbuf> Content-Language: en-US From: James Clark In-Reply-To: <20250612143157.bu4vayvhieohdtbu@skbuf> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 12/06/2025 3:31 pm, Vladimir Oltean wrote: > On Thu, Jun 12, 2025 at 03:28:37PM +0100, James Clark wrote: >> >> >> On 12/06/2025 3:23 pm, Vladimir Oltean wrote: >>> On Thu, Jun 12, 2025 at 03:14:32PM +0100, James Clark wrote: >>>>> That's why I don't like the DMA mode in DSPI, it's still CPU-bound, >>>>> because the DMA buffers are very small (you can only provide one TX FIFO >>>>> worth of data per DMA transfer, rather than the whole buffer). >>>> >>>> Is that right? The FIFO size isn't used in any of the DMA codepaths, it >>>> looks like the whole DMA buffer is filled before initiating the transfer. >>>> And we increase the buffer to 4k in this patchset to fully use the existing >>>> allocation. >>> >>> Uhm, yeah, no? >>> >>> dspi_dma_xfer(): >>> >>> while (dspi->len) { >>> dspi->words_in_flight = dspi->len / dspi->oper_word_size; >>> if (dspi->words_in_flight > dspi->devtype_data->fifo_size) >>> dspi->words_in_flight = dspi->devtype_data->fifo_size; >>> dspi_next_xfer_dma_submit(); >>> } >> >> Right but that's before the change in this patchset to use the whole page >> that was allocated, hence the next bit: >> >>> And we increase the buffer to 4k in this patchset to fully use the >> existing allocation. >> >> We were allocating for the size of the FIFO (multiplied by two to hold the >> control words), but dma_alloc_coherent() will be backed by a whole page >> anyway, even if you only ask for a few bytes. >> >> After changing that to make use of the full allocation the FIFO length is no >> longer involved. > > Ok, I haven't walked through patch 3 yet, I didn't realize it would be > changing that. I will want to test it on LS1028A. Yeah testing it somewhere else would be good. Maybe there is some limitation there about the max size of the DMA transfer, but I didn't see it. I realise the tense in my original message may have been a bit confusing. I was mixing up the existing code and proposed changes...