From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mout-p-101.mailbox.org (mout-p-101.mailbox.org [80.241.56.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6A7E2E8B85 for ; Fri, 17 Oct 2025 16:51:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.151 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760719866; cv=none; b=PQ2N+o/0XVQouseehnMO5TGZlfM5OH7QpQOWvQ3UZtNG3r0MYQN7uqd1hlEHh5V6GR5cpapsbZr4YVC0OIHY2XUXtMPUakNITdA+wyM7xgLJmd02TqkiS17urHt4/CC9CyqaYH452rsf8jdK1XCxcPlIsnGwjWW2SCpk3N3klGI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760719866; c=relaxed/simple; bh=jiYZwSUFJloZCDoz0GoZrQ9olAkcacA8Tzq/V9VuUZI=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=h8UGOJseeHUHwkY26JJOR+CH9BI38z3XLyDOseAmY/Do1WTGmtVG4E21h4jr5pXY+HTAqI3lshNjJh3yWbFIlH7nvsvsQ8U3jgL7qGxTI/WwoSf4hu/Xz6r5xX3IRnTUYBuizcEXluy9Pk6eDOp1qv8ZlhsFgaxJnEYZOAQmGfE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=ri3EMDsZ; arc=none smtp.client-ip=80.241.56.151 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="ri3EMDsZ" Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:b231:465::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-101.mailbox.org (Postfix) with ESMTPS id 4cp9nK2L1Jz9sSq; Fri, 17 Oct 2025 18:51:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1760719861; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jJsJIIBmyS44r/Za6Ww7u8aRde5yPPmd2EJgiWuqZok=; b=ri3EMDsZEN4UnyNu0+7sYCnpRhI59tlwCE72BMClrJG5Z/9VF3E0TFTmdsWE93bSKc4gE7 hhs2WbanfCytWk3dPq2JFhRQEvXftZxx1UYwFG60B/mLGbhhsMPKLkMeRKu/tqRZflxcxk 8Hf2wvQ4HzRjc9duTrppLkVLAHgai6wntue296XwapLUXyZUSLeEQtOJBS5RMjRAzDqi0T cQXsbhNO03cUtPukXFA86VbXx2WuUpqDmoX1f3ltipWOY3Sd8NjQoKGJjOmcjXv1XaBzXc 8ECMjKEBoEfQcSen58Q+dgonWGKRG+xvzEcbsFzqjErR0jqaNLLqlnMKeersDw== Message-ID: <49a97a81-f5db-40c7-83ae-2e12b790a6ae@mailbox.org> Date: Fri, 17 Oct 2025 17:18:16 +0200 Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH 03/39] dt-bindings: display: imx: Document i.MX95 Display Controller processing units To: Liu Ying , Frank Li Cc: dri-devel@lists.freedesktop.org, Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Laurent Pinchart , Lucas Stach , Peng Fan , Pengutronix Kernel Team , Rob Herring , Shawn Guo , Thomas Zimmermann , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org References: <20251011170213.128907-1-marek.vasut@mailbox.org> <20251011170213.128907-4-marek.vasut@mailbox.org> <260b4db1-c02a-48a0-baf8-5e217c729824@mailbox.org> Content-Language: en-US From: Marek Vasut In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-MBO-RS-ID: 06fa1a62a3227d44521 X-MBO-RS-META: 4jmhrbazn39p7xypji99r43776hhwgqg On 10/16/25 4:28 AM, Liu Ying wrote: Hello Liu, > Have you got i.MX95 DC IP spec? If no, then it would be difficult for you to > write DT bindings for all i.MX95 DC units. Note that this is something > necessary to do. Nope, still waiting for those. > And, a bit more information about display pipelines in i.MX95 display domain: > > Dither -> pixel interleaver -> pixel link loopback -> camera domain > -> pixel link -> MIPI DSI controller > -> pixel mapper(LDB) > > Note that NXP downstream kernel wrongly adds pixel link between pixel > interleaver and pixel mapper due to ambiguous i.MX95 TRM. Is my understanding correct, that the Dither Unit ~= Display Engine ?