From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCC0B125B9; Wed, 16 Oct 2024 21:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729115397; cv=none; b=Y6tNmbfFsD9g6YS3EvPDzvHH1an1Ypq7yeA9e/3a9j8Ok2WeDMq1DGpA5PsbLt0Ba/IMKX9UMwTwBEePSzigr1Xk9DNpJRTt1drVYo2eYfPM8vkv0rJRLWZBzkGAh77O4dY82TBQdPENEsjU7kPnkjq1HqWEeK+MdpSiBG6PFdY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729115397; c=relaxed/simple; bh=Hp+H7yoAyapEdhvaBlQzGXZZGhKUy3jtoMpeNHH/Y0o=; h=Message-ID:Content-Type:MIME-Version:In-Reply-To:References: Subject:From:Cc:To:Date; b=eFRW10rye4ej2OB/r07pw9dhxaX8KtxZtG5nS+NkQhnoMkzNd0hcplcDq8h/OwND9LoDOh4NnFBohHtjvjCQc9hJNYSrw+JOC8RVlzElbgKQFEyqYVQM0FDpnL3K7CHrZ3otwdpMxfkNxRmSBOgkMJqkJEljz1zFA3swU4sB5vc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ab5xwJqa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ab5xwJqa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2FC69C4CEC5; Wed, 16 Oct 2024 21:49:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729115397; bh=Hp+H7yoAyapEdhvaBlQzGXZZGhKUy3jtoMpeNHH/Y0o=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=ab5xwJqainPvNFCX2PalKHOxzA3L3nK5zwFARgT7/XEdijZX9hA/UkoSQkW7mAhg7 d+GCqVvXl2YVMFIF6IQHziwyR5aQbcUH/Om7q9iPTziNPrO6mN4HclkwRDecstvltL PGbCqzvHo26Yka4ACeSDyJL7mGbTcsMmpnv8AXQ36QeRbTgTRsJ9cSZzJIqWLVanpl IRmnWcCWUUGWAuah2wOXkmrZT6F6tgPWmOp9yA96Al8enfsKSM+zVQUSkYfoSDLFlw a6q05U84twcZ+PLbdsOsZ5ToLR5vT8WtU61x+hrddn0ZtNeCqin6YLT1lOwGVjFbLR TgafhqGvGqgmw== Message-ID: <4c7956afc86ea05f07b25d98ffb5b80c.sboyd@kernel.org> Content-Type: text/plain; charset="utf-8" Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20241014-imx-clk-v1-v1-4-ee75876d3102@nxp.com> References: <20241014-imx-clk-v1-v1-0-ee75876d3102@nxp.com> <20241014-imx-clk-v1-v1-4-ee75876d3102@nxp.com> Subject: Re: [PATCH 4/4] clk: imx: fracn-gppll: fix pll power up From: Stephen Boyd Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan , Jacky Bai To: Abel Vesa , Aisheng Dong , Fabio Estevam , Michael Turquette , Peng Fan (OSS) , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo Date: Wed, 16 Oct 2024 14:49:55 -0700 User-Agent: alot/0.10 Quoting Peng Fan (OSS) (2024-10-14 02:11:25) > From: Peng Fan >=20 > To i.MX93 which features dual Cortex-A55 cores and DSU, when using > writel_relaxed to write value to PLL registers, the value might be > buffered. To make sure the value has been written into the hardware, > using readl to read back the register could make sure the value > written into hardware. >=20 > current PLL power up flow can be simplified as below: > 1. writel_relaxed to set the PLL POWERUP bit; > 2. readl_poll_timeout to check the PLL lock bit: > a). timeout =3D ktime_add_us(ktime_get(), timeout_us); > b). readl the pll the lock reg; > c). check if the pll lock bit ready > d). check if timeout >=20 > But in some corner cases, both the write in step 1 and read in > step 2 will be blocked by other bus transaction in the SoC for a > long time, saying the value into real hardware is just before step b). > That means the timeout counting has begins for quite sometime since > step a), but value still not written into real hardware until bus > released just at a point before step b). >=20 > Then there maybe chances that the pll lock bit is not ready > when readl done but the timeout happens. readl_poll_timeout will > err return due to timeout. To avoid such unexpected failure, > read back the reg to make sure the write has been done in HW > reg. >=20 > Introduce fence_write for this purpose. Please just write out the readl() instead of introducing a bespoke macro that isn't generic for all architectures.