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Fri, 19 Sep 2025 10:22:51 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: AneuvEk2E7Kg Date: Fri, 19 Sep 2025 16:22:20 +0200 From: "Arnd Bergmann" To: "Geert Uytterhoeven" Cc: "Jason Gunthorpe" , ksummit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-mips@vger.kernel.org, linux-mm@kvack.org, imx@lists.linux.dev, "Christophe Leroy" , "Richard Weinberger" , "Lucas Stach" , "Linus Walleij" , "Geert Uytterhoeven" , "Ankur Arora" , "David Hildenbrand" , "Mike Rapoport" , "Lorenzo Stoakes" , "Matthew Wilcox" , "Andrew Morton" , "Liam R. Howlett" , "Vlastimil Babka" , "Suren Baghdasaryan" , "Ira Weiny" , "Nishanth Menon" , =?UTF-8?Q?Heiko_St=C3=BCbner?= , "Alexander Sverdlin" , "Chester A. Unal" , "Sergio Paracuellos" , "Andreas Larsson" Message-Id: <547dcb81-434d-4910-aa7c-1d69019fcb3d@app.fastmail.com> In-Reply-To: References: <4ff89b72-03ff-4447-9d21-dd6a5fe1550f@app.fastmail.com> <20250917125951.GA1390993@nvidia.com> <02b0f383-1c43-4eeb-a76f-830c2970b833@app.fastmail.com> Subject: Re: [TECH TOPIC] Reaching consensus on CONFIG_HIGHMEM phaseout Content-Type: text/plain Content-Transfer-Encoding: 7bit On Fri, Sep 19, 2025, at 09:17, Geert Uytterhoeven wrote: > On Thu, 18 Sept 2025 at 15:13, Arnd Bergmann wrote: >> On Wed, Sep 17, 2025, at 14:59, Jason Gunthorpe wrote: >> > On Tue, Sep 09, 2025 at 11:23:37PM +0200, Arnd Bergmann wrote: > >> * Microchip SAM9x7 is the newest ARMv5 chip, clearly does >> get kernel updates, and the only one I can think of with >> DDR3 support, but seems to be limited to 256MB total memory. > > Are they limited to DDR3? > > IIRC, someone (you? ;-) told me at ELCE that Microchip keeps on spinning > new variants of old SoCs, to accommodate the changing DDR landscape > and market. So perhaps they also accept larger RAM sizes? Yes, that was me. The previous SAM9x60 was released in 2020 and I think that one was an upgrade to a smaller process node, raising the clock frequency to 600MHz and adding more modern peripherals, but I see now that this used the same SDRAM/LPDDR/DDR2 memory controller as previous chips, with a limit of 128MB total DRAM. SAM9X7 in 2023 added DDR3 mode with up to 256MB according to the datasheet, no idea why they chose not to support more, since a 32-bit wide DDR3 bus should allow up to 1GB with two 256Mbit x16 chips that are widely available, or even more using expensive 512Mbit x16 or 1Gbit x8 chips. Arnd