Re: [PATCH v1] serial: imx: only set receiver level if it is zero

[Jiri Slaby <jirislaby@kernel.org>]

On 03. 07. 24, 13:25, Stefan Eichenberger wrote:
> From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
> 
> With commit a81dbd0463ec ("serial: imx: set receiver level before
> starting uart") we set the receiver level to its default value. This
> caused a regression when using SDMA, where the receiver level is 9
> instead of 8 (default). This change will first check if the receiver
> level is zero and only then set it to the default. This still avoids the
> interrupt storm when the receiver level is zero.
> 
> Fixes: a81dbd0463ec ("serial: imx: set receiver level before starting uart")
> Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
> ---
>   drivers/tty/serial/imx.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
> index f4f40c9373c2f..e22be8f45c93e 100644
> --- a/drivers/tty/serial/imx.c
> +++ b/drivers/tty/serial/imx.c
> @@ -120,6 +120,7 @@
>   #define UCR4_OREN	(1<<1)	/* Receiver overrun interrupt enable */
>   #define UCR4_DREN	(1<<0)	/* Recv data ready interrupt enable */
>   #define UFCR_RXTL_SHF	0	/* Receiver trigger level shift */
> +#define UFCR_RXTL_MASK	0x3F	/* Receiver trigger 6 bits wide */
>   #define UFCR_DCEDTE	(1<<6)	/* DCE/DTE mode select */
>   #define UFCR_RFDIV	(7<<7)	/* Reference freq divider mask */

All these should be converted to BIT() and GENMASK(). Then, 
UFCR_RXTL_MASK should be obviously GENMASK(5, 0).

UFCR_RXTL_SHF is unused (and unneeded) BTW.

>   #define UFCR_RFDIV_REG(x)	(((x) < 7 ? 6 - (x) : 6) << 7)

thanks,
-- 
js