From: Tudor Ambarus <tudor.ambarus@linaro.org>
To: Haibo Chen <haibo.chen@nxp.com>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev
Subject: Re: [PATCH 1/4] mtd: spi-nor: micron-st: rename the die_late_init functions
Date: Mon, 10 Nov 2025 08:32:00 +0200 [thread overview]
Message-ID: <85b973b1-ec1a-4508-a9f5-fbf6917eab85@linaro.org> (raw)
In-Reply-To: <20251110-nor-v1-1-cde50c81db05@nxp.com>
On 11/10/25 6:02 AM, Haibo Chen wrote:
> st_nor_two/four_die_late_init() also suit for micron chips, so
> rename to micron_st_nor_two/four_die_late_init().
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
> drivers/mtd/spi-nor/micron-st.c | 70 ++++++++++++++++++++---------------------
> 1 file changed, 35 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index 187239ccd549510c6e9a6eacf4ae41158287e077..92eb14ca76c57f29ece1edb3fe652c56d1c2888f 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -127,6 +127,38 @@ static int micron_st_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
> micron_st_nor_octal_dtr_dis(nor);
> }
>
> +static int micron_st_nor_four_die_late_init(struct spi_nor *nor)
> +{
> + struct spi_nor_flash_parameter *params = nor->params;
> +
> + params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
> + params->n_dice = 4;
> +
> + /*
> + * Unfortunately the die erase opcode does not have a 4-byte opcode
> + * correspondent for these flashes. The SFDP 4BAIT table fails to
> + * consider the die erase too. We're forced to enter in the 4 byte
> + * address mode in order to benefit of the die erase.
> + */
> + return spi_nor_set_4byte_addr_mode(nor, true);
> +}
> +
> +static int micron_st_nor_two_die_late_init(struct spi_nor *nor)
> +{
> + struct spi_nor_flash_parameter *params = nor->params;
> +
> + params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
> + params->n_dice = 2;
> +
> + /*
> + * Unfortunately the die erase opcode does not have a 4-byte opcode
> + * correspondent for these flashes. The SFDP 4BAIT table fails to
> + * consider the die erase too. We're forced to enter in the 4 byte
> + * address mode in order to benefit of the die erase.
> + */
> + return spi_nor_set_4byte_addr_mode(nor, true);
> +}
I see you also moved the methods a bit up, maybe to have all micron_st methods
in one place. Specify this in the commit message to spare reviewers of checking
bit-to-bit exact move.
With that:
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> +
> static void mt35xu512aba_default_init(struct spi_nor *nor)
> {
> nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr;
> @@ -193,48 +225,16 @@ static const struct spi_nor_fixups mt25qu512a_fixups = {
> .post_bfpt = mt25qu512a_post_bfpt_fixup,
> };
>
> -static int st_nor_four_die_late_init(struct spi_nor *nor)
> -{
> - struct spi_nor_flash_parameter *params = nor->params;
> -
> - params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
> - params->n_dice = 4;
> -
> - /*
> - * Unfortunately the die erase opcode does not have a 4-byte opcode
> - * correspondent for these flashes. The SFDP 4BAIT table fails to
> - * consider the die erase too. We're forced to enter in the 4 byte
> - * address mode in order to benefit of the die erase.
> - */
> - return spi_nor_set_4byte_addr_mode(nor, true);
> -}
> -
> -static int st_nor_two_die_late_init(struct spi_nor *nor)
> -{
> - struct spi_nor_flash_parameter *params = nor->params;
> -
> - params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
> - params->n_dice = 2;
> -
> - /*
> - * Unfortunately the die erase opcode does not have a 4-byte opcode
> - * correspondent for these flashes. The SFDP 4BAIT table fails to
> - * consider the die erase too. We're forced to enter in the 4 byte
> - * address mode in order to benefit of the die erase.
> - */
> - return spi_nor_set_4byte_addr_mode(nor, true);
> -}
> -
> static const struct spi_nor_fixups n25q00_fixups = {
> - .late_init = st_nor_four_die_late_init,
> + .late_init = micron_st_nor_four_die_late_init,
> };
>
> static const struct spi_nor_fixups mt25q01_fixups = {
> - .late_init = st_nor_two_die_late_init,
> + .late_init = micron_st_nor_two_die_late_init,
> };
>
> static const struct spi_nor_fixups mt25q02_fixups = {
> - .late_init = st_nor_four_die_late_init,
> + .late_init = micron_st_nor_four_die_late_init,
> };
>
> static const struct flash_info st_nor_parts[] = {
>
next prev parent reply other threads:[~2025-11-10 6:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-10 4:02 [PATCH 0/4] mtd: spi-nor: micron-st: add die erase for micron spi nor chip Haibo Chen
2025-11-10 4:02 ` [PATCH 1/4] mtd: spi-nor: micron-st: rename the die_late_init functions Haibo Chen
2025-11-10 6:32 ` Tudor Ambarus [this message]
2025-11-10 4:02 ` [PATCH 2/4] mtd: spi-nor: micron-st: add die erase for mt35xu512aba Haibo Chen
2025-11-10 6:38 ` Tudor Ambarus
2025-11-11 7:36 ` Bough Chen
2025-11-10 4:02 ` [PATCH 3/4] mtd: spi-nor: micron-st: add mt35xu01gbba support Haibo Chen
2025-11-10 6:42 ` Tudor Ambarus
2025-11-11 7:54 ` Bough Chen
2025-11-11 8:23 ` Tudor Ambarus
2025-11-10 4:02 ` [PATCH 4/4] mtd: spi-nor: micron-st: enable 8D-8D-8D mode and die erase for mt35xu02gcba Haibo Chen
2025-11-10 6:45 ` Tudor Ambarus
2025-11-11 8:00 ` Bough Chen
2025-11-11 8:29 ` Tudor Ambarus
2025-11-11 8:33 ` Bough Chen
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