Re: [EXT] I2C_IMX support for i.MX8MP

Richard Leitner
2022-08-18T13:47:34Z

On Thu, Aug 18, 2022 at 07:54:04AM -0500, David Wolfson wrote:
> On Thu, Aug 18, 2022 at 11:59:41AM +0000, Shenwei Wang wrote:
> > Hi Richard,
> >
> > Nothing is hidden here. That is PAD control register, and should be documented in the IOMUXC and PIN Control section in the RM.
> >
>
> Checking the IOMUX and PADs' settings is the first step when enabling
> an interface.

Sure, that's what I've done. Nonetheless the "8.2.4.280
SW_PAD_CTL_PAD_I2C3_SCL SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL)" section in the IMX8MPRM says bit 30 is
reserved.

So does "8.2.4.128 SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL)".

Maybe I'm just too dumb do find it... So it would be really helpful if
you could please give a pointer where to find that documentation?

Thanks & regards;rl

>
> David
>