* [PATCH] arm64: dts: s32g: add RTC node
@ 2025-05-26 16:21 Ciprian Costea
2025-05-26 18:20 ` Matthias Brugger
2025-06-19 7:55 ` Shawn Guo
0 siblings, 2 replies; 7+ messages in thread
From: Ciprian Costea @ 2025-05-26 16:21 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: NXP S32 Linux Team, Pengutronix Kernel Team, linux-arm-kernel,
imx, devicetree, linux-kernel, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Eric Chanudet, Ciprian Marian Costea
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
system suspend.
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index fa054bfe7d5c..39d12422e3f3 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -114,6 +114,14 @@ soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
+ rtc0: rtc@40060000 {
+ compatible = "nxp,s32g2-rtc";
+ reg = <0x40060000 0x1000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 54>, <&clks 55>;
+ clock-names = "ipg", "source0";
+ };
+
pinctrl: pinctrl@4009c240 {
compatible = "nxp,s32g2-siul2-pinctrl";
/* MSCR0-MSCR101 registers on siul2_0 */
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index b4226a9143c8..e71b80e048dc 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -171,6 +171,15 @@ soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
+ rtc0: rtc@40060000 {
+ compatible = "nxp,s32g3-rtc",
+ "nxp,s32g2-rtc";
+ reg = <0x40060000 0x1000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 54>, <&clks 55>;
+ clock-names = "ipg", "source0";
+ };
+
pinctrl: pinctrl@4009c240 {
compatible = "nxp,s32g2-siul2-pinctrl";
/* MSCR0-MSCR101 registers on siul2_0 */
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] arm64: dts: s32g: add RTC node
2025-05-26 16:21 [PATCH] arm64: dts: s32g: add RTC node Ciprian Costea
@ 2025-05-26 18:20 ` Matthias Brugger
2025-06-19 7:48 ` Ciprian Marian Costea
2025-06-19 7:55 ` Shawn Guo
1 sibling, 1 reply; 7+ messages in thread
From: Matthias Brugger @ 2025-05-26 18:20 UTC (permalink / raw)
To: Ciprian Costea, Chester Lin, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: NXP S32 Linux Team, Pengutronix Kernel Team, linux-arm-kernel,
imx, devicetree, linux-kernel, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Eric Chanudet
On 26/05/2025 18:21, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
> system suspend.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index fa054bfe7d5c..39d12422e3f3 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -114,6 +114,14 @@ soc@0 {
> #size-cells = <1>;
> ranges = <0 0 0 0x80000000>;
>
> + rtc0: rtc@40060000 {
> + compatible = "nxp,s32g2-rtc";
> + reg = <0x40060000 0x1000>;
> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 54>, <&clks 55>;
> + clock-names = "ipg", "source0";
> + };
> +
> pinctrl: pinctrl@4009c240 {
> compatible = "nxp,s32g2-siul2-pinctrl";
> /* MSCR0-MSCR101 registers on siul2_0 */
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index b4226a9143c8..e71b80e048dc 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -171,6 +171,15 @@ soc@0 {
> #size-cells = <1>;
> ranges = <0 0 0 0x80000000>;
>
> + rtc0: rtc@40060000 {
> + compatible = "nxp,s32g3-rtc",
> + "nxp,s32g2-rtc";
> + reg = <0x40060000 0x1000>;
> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 54>, <&clks 55>;
> + clock-names = "ipg", "source0";
> + };
> +
> pinctrl: pinctrl@4009c240 {
> compatible = "nxp,s32g2-siul2-pinctrl";
> /* MSCR0-MSCR101 registers on siul2_0 */
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] arm64: dts: s32g: add RTC node
2025-05-26 18:20 ` Matthias Brugger
@ 2025-06-19 7:48 ` Ciprian Marian Costea
0 siblings, 0 replies; 7+ messages in thread
From: Ciprian Marian Costea @ 2025-06-19 7:48 UTC (permalink / raw)
To: Matthias Brugger, Chester Lin, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: NXP S32 Linux Team, Pengutronix Kernel Team, linux-arm-kernel,
imx, devicetree, linux-kernel, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Eric Chanudet
On 5/26/2025 9:20 PM, Matthias Brugger wrote:
>
>
> On 26/05/2025 18:21, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
>> system suspend.
>>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Reviewed-by: Matthias Brugger <mbrugger@suse.com>
>
Hello Shawn,
Sorry for bothering. Can you please provide feedback with respect to the
status of this S32G2/S32G3 DTS patch ?
Regards,
Ciprian
>> ---
>> arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
>> arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
>> 2 files changed, 17 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/
>> boot/dts/freescale/s32g2.dtsi
>> index fa054bfe7d5c..39d12422e3f3 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> @@ -114,6 +114,14 @@ soc@0 {
>> #size-cells = <1>;
>> ranges = <0 0 0 0x80000000>;
>> + rtc0: rtc@40060000 {
>> + compatible = "nxp,s32g2-rtc";
>> + reg = <0x40060000 0x1000>;
>> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 54>, <&clks 55>;
>> + clock-names = "ipg", "source0";
>> + };
>> +
>> pinctrl: pinctrl@4009c240 {
>> compatible = "nxp,s32g2-siul2-pinctrl";
>> /* MSCR0-MSCR101 registers on siul2_0 */
>> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/
>> boot/dts/freescale/s32g3.dtsi
>> index b4226a9143c8..e71b80e048dc 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
>> @@ -171,6 +171,15 @@ soc@0 {
>> #size-cells = <1>;
>> ranges = <0 0 0 0x80000000>;
>> + rtc0: rtc@40060000 {
>> + compatible = "nxp,s32g3-rtc",
>> + "nxp,s32g2-rtc";
>> + reg = <0x40060000 0x1000>;
>> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 54>, <&clks 55>;
>> + clock-names = "ipg", "source0";
>> + };
>> +
>> pinctrl: pinctrl@4009c240 {
>> compatible = "nxp,s32g2-siul2-pinctrl";
>> /* MSCR0-MSCR101 registers on siul2_0 */
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: s32g: add RTC node
2025-05-26 16:21 [PATCH] arm64: dts: s32g: add RTC node Ciprian Costea
2025-05-26 18:20 ` Matthias Brugger
@ 2025-06-19 7:55 ` Shawn Guo
1 sibling, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2025-06-19 7:55 UTC (permalink / raw)
To: Ciprian Costea
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, NXP S32 Linux Team, Pengutronix Kernel Team,
linux-arm-kernel, imx, devicetree, linux-kernel, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo, Eric Chanudet
On Mon, May 26, 2025 at 07:21:40PM +0300, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
> system suspend.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Applied, thanks!
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] arm64: dts: s32g: add RTC node
@ 2025-05-26 16:29 Ciprian Costea
2025-05-26 16:32 ` Ciprian Marian Costea
2025-05-28 15:41 ` Frank Li
0 siblings, 2 replies; 7+ messages in thread
From: Ciprian Costea @ 2025-05-26 16:29 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-kernel, Christophe Lizzi, Alberto Ruiz, Enric Balletbo,
Eric Chanudet, imx, Ciprian Marian Costea
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
system suspend.
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index fa054bfe7d5c..39d12422e3f3 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -114,6 +114,14 @@ soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
+ rtc0: rtc@40060000 {
+ compatible = "nxp,s32g2-rtc";
+ reg = <0x40060000 0x1000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 54>, <&clks 55>;
+ clock-names = "ipg", "source0";
+ };
+
pinctrl: pinctrl@4009c240 {
compatible = "nxp,s32g2-siul2-pinctrl";
/* MSCR0-MSCR101 registers on siul2_0 */
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index b4226a9143c8..e71b80e048dc 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -171,6 +171,15 @@ soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
+ rtc0: rtc@40060000 {
+ compatible = "nxp,s32g3-rtc",
+ "nxp,s32g2-rtc";
+ reg = <0x40060000 0x1000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 54>, <&clks 55>;
+ clock-names = "ipg", "source0";
+ };
+
pinctrl: pinctrl@4009c240 {
compatible = "nxp,s32g2-siul2-pinctrl";
/* MSCR0-MSCR101 registers on siul2_0 */
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] arm64: dts: s32g: add RTC node
2025-05-26 16:29 Ciprian Costea
@ 2025-05-26 16:32 ` Ciprian Marian Costea
2025-05-28 15:41 ` Frank Li
1 sibling, 0 replies; 7+ messages in thread
From: Ciprian Marian Costea @ 2025-05-26 16:32 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-kernel, Christophe Lizzi, Alberto Ruiz, Enric Balletbo,
Eric Chanudet, imx
On 5/26/2025 7:29 PM, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
> system suspend.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index fa054bfe7d5c..39d12422e3f3 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -114,6 +114,14 @@ soc@0 {
> #size-cells = <1>;
> ranges = <0 0 0 0x80000000>;
>
> + rtc0: rtc@40060000 {
> + compatible = "nxp,s32g2-rtc";
> + reg = <0x40060000 0x1000>;
> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 54>, <&clks 55>;
> + clock-names = "ipg", "source0";
> + };
> +
> pinctrl: pinctrl@4009c240 {
> compatible = "nxp,s32g2-siul2-pinctrl";
> /* MSCR0-MSCR101 registers on siul2_0 */
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index b4226a9143c8..e71b80e048dc 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -171,6 +171,15 @@ soc@0 {
> #size-cells = <1>;
> ranges = <0 0 0 0x80000000>;
>
> + rtc0: rtc@40060000 {
> + compatible = "nxp,s32g3-rtc",
> + "nxp,s32g2-rtc";
> + reg = <0x40060000 0x1000>;
> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 54>, <&clks 55>;
> + clock-names = "ipg", "source0";
> + };
> +
> pinctrl: pinctrl@4009c240 {
> compatible = "nxp,s32g2-siul2-pinctrl";
> /* MSCR0-MSCR101 registers on siul2_0 */
Wrong audience. Please ignore.
Regards,
Ciprian
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] arm64: dts: s32g: add RTC node
2025-05-26 16:29 Ciprian Costea
2025-05-26 16:32 ` Ciprian Marian Costea
@ 2025-05-28 15:41 ` Frank Li
1 sibling, 0 replies; 7+ messages in thread
From: Frank Li @ 2025-05-28 15:41 UTC (permalink / raw)
To: Ciprian Costea
Cc: Shawn Guo, linux-kernel, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Eric Chanudet, imx
On Mon, May 26, 2025 at 07:29:53PM +0300, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
> system suspend.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index fa054bfe7d5c..39d12422e3f3 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -114,6 +114,14 @@ soc@0 {
> #size-cells = <1>;
> ranges = <0 0 0 0x80000000>;
>
> + rtc0: rtc@40060000 {
> + compatible = "nxp,s32g2-rtc";
> + reg = <0x40060000 0x1000>;
> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 54>, <&clks 55>;
> + clock-names = "ipg", "source0";
> + };
> +
> pinctrl: pinctrl@4009c240 {
> compatible = "nxp,s32g2-siul2-pinctrl";
> /* MSCR0-MSCR101 registers on siul2_0 */
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index b4226a9143c8..e71b80e048dc 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -171,6 +171,15 @@ soc@0 {
> #size-cells = <1>;
> ranges = <0 0 0 0x80000000>;
>
> + rtc0: rtc@40060000 {
> + compatible = "nxp,s32g3-rtc",
> + "nxp,s32g2-rtc";
> + reg = <0x40060000 0x1000>;
> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 54>, <&clks 55>;
> + clock-names = "ipg", "source0";
> + };
> +
> pinctrl: pinctrl@4009c240 {
> compatible = "nxp,s32g2-siul2-pinctrl";
> /* MSCR0-MSCR101 registers on siul2_0 */
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-06-19 7:55 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2025-05-26 16:21 [PATCH] arm64: dts: s32g: add RTC node Ciprian Costea
2025-05-26 18:20 ` Matthias Brugger
2025-06-19 7:48 ` Ciprian Marian Costea
2025-06-19 7:55 ` Shawn Guo
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2025-05-26 16:29 Ciprian Costea
2025-05-26 16:32 ` Ciprian Marian Costea
2025-05-28 15:41 ` Frank Li
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