[PATCH 1/2] arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed

[PATCH 1/2] arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed

[Adam Ford]

The reference manual for the i.MX8MM states the clock rate in
MMC mode is 1/2 of the input clock, therefore to properly run
at HS400 rates, the input clock must be 400MHz to operate at
200MHz.  Currently the clock is set to 200MHz which is half the
rate it should be, so the throughput is half of what it should be
for HS400 operation.

Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit")
Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
index 21bcd82fd092..8287a7f66ed3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
@@ -294,6 +294,8 @@ &usdhc3 {
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
+	assigned-clock-rates = <400000000>;
 	bus-width = <8>;
 	non-removable;
 	status = "okay";
-- 
2.48.1

[PATCH 2/2] arm64: dts: imx8mn-beacon: Fix HS400 USDHC clock speed

[Adam Ford]

The reference manual for the i.MX8MN states the clock rate in
MMC mode is 1/2 of the input clock, therefore to properly run
at HS400 rates, the input clock must be 400MHz to operate at
200MHz.  Currently the clock is set to 200MHz which is half the
rate it should be, so the throughput is half of what it should be
for HS400 operation.

Fixes: 36ca3c8ccb53 ("arm64: dts: imx: Add Beacon i.MX8M Nano development kit")
Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
index 67a99383a632..917b7d0007a7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
@@ -305,6 +305,8 @@ &usdhc3 {
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC3>;
+	assigned-clock-rates = <400000000>;
 	bus-width = <8>;
 	non-removable;
 	status = "okay";
-- 
2.48.1

Re: [PATCH 2/2] arm64: dts: imx8mn-beacon: Fix HS400 USDHC clock speed

[Fabio Estevam]

On Fri, Jun 20, 2025 at 6:34 PM Adam Ford <aford173@gmail.com> wrote:
>
> The reference manual for the i.MX8MN states the clock rate in
> MMC mode is 1/2 of the input clock, therefore to properly run
> at HS400 rates, the input clock must be 400MHz to operate at
> 200MHz.  Currently the clock is set to 200MHz which is half the
> rate it should be, so the throughput is half of what it should be
> for HS400 operation.
>
> Fixes: 36ca3c8ccb53 ("arm64: dts: imx: Add Beacon i.MX8M Nano development kit")
> Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

Re: [PATCH 1/2] arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed

[Tim Harvey]

On Fri, Jun 20, 2025 at 2:52 PM Adam Ford <aford173@gmail.com> wrote:
>
> The reference manual for the i.MX8MM states the clock rate in
> MMC mode is 1/2 of the input clock, therefore to properly run
> at HS400 rates, the input clock must be 400MHz to operate at
> 200MHz.  Currently the clock is set to 200MHz which is half the
> rate it should be, so the throughput is half of what it should be
> for HS400 operation.
>
> Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit")
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> index 21bcd82fd092..8287a7f66ed3 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> @@ -294,6 +294,8 @@ &usdhc3 {
>         pinctrl-0 = <&pinctrl_usdhc3>;
>         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
>         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> +       assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
> +       assigned-clock-rates = <400000000>;
>         bus-width = <8>;
>         non-removable;
>         status = "okay";
> --
> 2.48.1
>
>

Hi Adam,

This caught my interest. Where in the IMX8MMRM do you see this and
would it also apply to the IMX8MP? (You've patched your IMX8MM and
IMX8MN boards).

Have you encountered any issues when running eMMC at HS400 due to this
or is it just something you noticed in the RM more recently like with
my recent patch that lowers SPI clock due to an obscure RM note [1]

Best Regards,

Tim
[1] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=965976&archive=both

Re: [PATCH 1/2] arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed

[Adam Ford]

On Fri, Jun 27, 2025 at 12:56 PM Tim Harvey <tharvey@gateworks.com> wrote:
>
> On Fri, Jun 20, 2025 at 2:52 PM Adam Ford <aford173@gmail.com> wrote:
> >
> > The reference manual for the i.MX8MM states the clock rate in
> > MMC mode is 1/2 of the input clock, therefore to properly run
> > at HS400 rates, the input clock must be 400MHz to operate at
> > 200MHz.  Currently the clock is set to 200MHz which is half the
> > rate it should be, so the throughput is half of what it should be
> > for HS400 operation.
> >
> > Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit")
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> > index 21bcd82fd092..8287a7f66ed3 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> > @@ -294,6 +294,8 @@ &usdhc3 {
> >         pinctrl-0 = <&pinctrl_usdhc3>;
> >         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> >         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> > +       assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
> > +       assigned-clock-rates = <400000000>;
> >         bus-width = <8>;
> >         non-removable;
> >         status = "okay";
> > --
> > 2.48.1
> >
> >
>
> Hi Adam,
>
> This caught my interest. Where in the IMX8MMRM do you see this and
> would it also apply to the IMX8MP? (You've patched your IMX8MM and
> IMX8MN boards).

My 8MP board already appears to be running at 400MHz, but I did check.
The reference I found was in the 8MM TRM, under 10.3.3.5 Clock
generator, there is a note:

CLK is different for the SDR and DDR modes.
- In the SDR mode, CLK is equal to the internal working clock (card_clk).
- In the DDR mode, CLK is equal to card_clk/2.

>
> Have you encountered any issues when running eMMC at HS400 due to this
> or is it just something you noticed in the RM more recently like with

One of my colleagues reported that the eMMC was running slower than he
expected, and I looked at the reference clock and noticed the 200MHz.
He asked if it needed to run 2x that since HS400 clocks on both edges.
I looked it up and found the note from above.  When I increased the
rate to 400MHz from 200MHz, the throughput doubled. I also noticed
some other boards, including the reference from NXP had the clock rate
set to 400MHz, so I don't think anything unreasonable.

adam

> my recent patch that lowers SPI clock due to an obscure RM note [1]
>
> Best Regards,
>
> Tim
> [1] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=965976&archive=both

Re: [PATCH 1/2] arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed

[Tim Harvey]

On Fri, Jun 27, 2025 at 11:40 AM Adam Ford <aford173@gmail.com> wrote:
>
> On Fri, Jun 27, 2025 at 12:56 PM Tim Harvey <tharvey@gateworks.com> wrote:
> >
> > On Fri, Jun 20, 2025 at 2:52 PM Adam Ford <aford173@gmail.com> wrote:
> > >
> > > The reference manual for the i.MX8MM states the clock rate in
> > > MMC mode is 1/2 of the input clock, therefore to properly run
> > > at HS400 rates, the input clock must be 400MHz to operate at
> > > 200MHz.  Currently the clock is set to 200MHz which is half the
> > > rate it should be, so the throughput is half of what it should be
> > > for HS400 operation.
> > >
> > > Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit")
> > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> > > index 21bcd82fd092..8287a7f66ed3 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> > > @@ -294,6 +294,8 @@ &usdhc3 {
> > >         pinctrl-0 = <&pinctrl_usdhc3>;
> > >         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> > >         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> > > +       assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
> > > +       assigned-clock-rates = <400000000>;
> > >         bus-width = <8>;
> > >         non-removable;
> > >         status = "okay";
> > > --
> > > 2.48.1
> > >
> > >
> >
> > Hi Adam,
> >
> > This caught my interest. Where in the IMX8MMRM do you see this and
> > would it also apply to the IMX8MP? (You've patched your IMX8MM and
> > IMX8MN boards).
>
> My 8MP board already appears to be running at 400MHz, but I did check.
> The reference I found was in the 8MM TRM, under 10.3.3.5 Clock
> generator, there is a note:
>
> CLK is different for the SDR and DDR modes.
> - In the SDR mode, CLK is equal to the internal working clock (card_clk).
> - In the DDR mode, CLK is equal to card_clk/2.
>
> >
> > Have you encountered any issues when running eMMC at HS400 due to this
> > or is it just something you noticed in the RM more recently like with
>
> One of my colleagues reported that the eMMC was running slower than he
> expected, and I looked at the reference clock and noticed the 200MHz.
> He asked if it needed to run 2x that since HS400 clocks on both edges.
> I looked it up and found the note from above.  When I increased the
> rate to 400MHz from 200MHz, the throughput doubled. I also noticed
> some other boards, including the reference from NXP had the clock rate
> set to 400MHz, so I don't think anything unreasonable.
>

Hi Adam,

The verbiage in the 'clock generator' section is not really easy to
understand but you're right, setting it to 400MHz also bumped the
performance on my boards. It looks like there are a lot of imx8m
boards that could likely benefit from this that are not already doing
so.

Check your imx8mp again, in my case (imx8mp-venice) sdhc3 was not
running at 400Mhz without the appropriate change - maybe yours is
running higher due to some other clock configuration you have.

I'll be patching my boards with this as well - thanks!

Best Regards,

Tim

Re: [PATCH 1/2] arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed

[Adam Ford]

On Fri, Jun 20, 2025 at 4:34 PM Adam Ford <aford173@gmail.com> wrote:
>
> The reference manual for the i.MX8MM states the clock rate in
> MMC mode is 1/2 of the input clock, therefore to properly run
> at HS400 rates, the input clock must be 400MHz to operate at
> 200MHz.  Currently the clock is set to 200MHz which is half the
> rate it should be, so the throughput is half of what it should be
> for HS400 operation.
>

Shawn and/or Fabio,

Any chance this can get reviewed and possibly applied for the next kernel?

thank you,

adam

> Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit")
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> index 21bcd82fd092..8287a7f66ed3 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> @@ -294,6 +294,8 @@ &usdhc3 {
>         pinctrl-0 = <&pinctrl_usdhc3>;
>         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
>         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> +       assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
> +       assigned-clock-rates = <400000000>;
>         bus-width = <8>;
>         non-removable;
>         status = "okay";
> --
> 2.48.1
>

Re: [PATCH 1/2] arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed

[Fabio Estevam]

On Fri, Jun 20, 2025 at 6:34 PM Adam Ford <aford173@gmail.com> wrote:
>
> The reference manual for the i.MX8MM states the clock rate in
> MMC mode is 1/2 of the input clock, therefore to properly run
> at HS400 rates, the input clock must be 400MHz to operate at
> 200MHz.  Currently the clock is set to 200MHz which is half the
> rate it should be, so the throughput is half of what it should be
> for HS400 operation.
>
> Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit")
> Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

Re: [PATCH 1/2] arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed

[Shawn Guo]

On Fri, Jun 20, 2025 at 04:34:45PM -0500, Adam Ford wrote:
> The reference manual for the i.MX8MM states the clock rate in
> MMC mode is 1/2 of the input clock, therefore to properly run
> at HS400 rates, the input clock must be 400MHz to operate at
> 200MHz.  Currently the clock is set to 200MHz which is half the
> rate it should be, so the throughput is half of what it should be
> for HS400 operation.
> 
> Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit")
> Signed-off-by: Adam Ford <aford173@gmail.com>

Applied both, thanks!