From: Shawn Guo <shawnguo2@yeah.net>
To: Tim Harvey <tharvey@gateworks.com>
Cc: linux-arm-kernel@lists.infradead.org,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH 1/7] arm64: dts: imx8mm-venice-gw700x: Increase HS400 USDHC clock speed
Date: Fri, 11 Jul 2025 16:04:24 +0800 [thread overview]
Message-ID: <aHDFiN8dn8zVnmZl@dragon> (raw)
In-Reply-To: <20250707201702.2930066-1-tharvey@gateworks.com>
On Mon, Jul 07, 2025 at 01:16:56PM -0700, Tim Harvey wrote:
> The IMX8M reference manuals indicate in the USDHC Clock generator section
> that the clock rate for DDR is 1/2 the input clock therefore HS400 rates
> clocked at 200Mhz require a 400Mhz SDHC clock.
>
> This showed about a 1.5x improvement in read performance for the eMMC's
> used on the various imx8m{m,n,p}-venice boards.
>
> Fixes: 6f30b27c5ef5 ("arm64: dts: imx8mm: Add Gateworks i.MX 8M Mini Development Kits")
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Applied all, thanks!
prev parent reply other threads:[~2025-07-11 8:04 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-07 20:16 [PATCH 1/7] arm64: dts: imx8mm-venice-gw700x: Increase HS400 USDHC clock speed Tim Harvey
2025-07-07 20:16 ` [PATCH 2/7] arm64: dts: imx8mp-venice-gw702x: " Tim Harvey
2025-07-07 20:16 ` [PATCH 3/7] arm64: dts: imx8mm-venice-gw7901: " Tim Harvey
2025-07-07 20:16 ` [PATCH 4/7] arm64: dts: imx8mm-venice-gw7902: " Tim Harvey
2025-07-07 20:17 ` [PATCH 5/7] arm64: dts: imx8mn-venice-gw7902: " Tim Harvey
2025-07-07 20:17 ` [PATCH 6/7] arm64: dts: imx8mm-venice-gw7903: " Tim Harvey
2025-07-07 20:17 ` [PATCH 7/7] arm64: dts: imx8mm-venice-gw7904: " Tim Harvey
2025-07-11 8:04 ` Shawn Guo [this message]
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