Re: Does dwc/pci-layerscape.c support AER?

[Brian Norris <briannorris@chromium.org>]

Hi Frank,

Thanks for the response.

On Thu, Jul 03, 2025 at 10:22:35PM -0400, Frank Li wrote:
> I saw AER and PME irq registed. But I have not seen irq increased. I am not
> sure how to inject an error to test it.

I've tested AER-like conditions via one of two ways:

1. force asserting PERST#, and then try to read a config register. This
   should generate Complection Timeouts at least, and possibly other
   errors. This method may not necessarily yield AER logs, as it may
   also reset the error reporting registers that the Linux AER driver
   would expect to read. But it probably should still trigger an
   interrupt.
   This depends on having access to PERST#; many SoCs provide this as a
   GPIO which you could potentially control, although I don't see this
   in the layerscape driver at the moment.
2. asserting HOT RESET in the DWC controller. This is especially
   implementation specific, as it depends on how (if at all) the hot
   reset signal is connected into your SoC.

Not sure if any of that helps you for testing. And maybe you want to
wire up your platform IRQs anyway.

Brian