[PATCH v2 0/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP

[PATCH v2 0/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP

[Dan Carpenter]

This driver provides a way to access the On Chip One-Time Programmable
Controller (OCOTP) on the s32g chipset.  There are three versions of this
chip but they're compatible.

v2:
I have fixed everything that people pointed out about version 1.

Sorry, Rob and Krzysztof, for the problems with the device tree YAML
file.  I had an issue with my dtschema installation and it's fixed now.

I also screwed up the From headers in v1.  I called git format-patch
without passing the --from argument.  I've fixed my scripts so that
won't happen again.  I also messed up the Signed-off by lines in patch
1 and 2.  Sorry!

My other mistakes were from not being a familiar enough with the
subsystem and those are addressed as well.  Especially re-writing the
driver using keepouts cut down a lot of lines of code.  I've tested it
and the results are the same before and after.

Ciprian Costea (2):
  dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
  nvmem: s32g-ocotp: Add driver for S32G OCOTP

Dan Carpenter (1):
  arm64: dts: s32g: Add device tree information for the OCOTP driver

 .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml  |  45 ++++++++
 arch/arm64/boot/dts/freescale/s32g2.dtsi      |   7 ++
 arch/arm64/boot/dts/freescale/s32g3.dtsi      |   7 ++
 drivers/nvmem/Kconfig                         |  10 ++
 drivers/nvmem/Makefile                        |   2 +
 drivers/nvmem/s32g-ocotp-nvmem.c              | 101 ++++++++++++++++++
 6 files changed, 172 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
 create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.c

-- 
2.47.2

[PATCH V2 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver

[Dan Carpenter]

Add the device tree information for the S32G On Chip One-Time
Programmable Controller (OCOTP) chip.

Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
v2: change "ocotp: ocotp@400a4000 {" to "ocotp: nvmem@400a4000 {"

 arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++
 arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++
 2 files changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 6a7cc7b33754..e8cfddabfc24 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -701,5 +701,12 @@ gic: interrupt-controller@50800000 {
 			interrupt-controller;
 			#interrupt-cells = <3>;
 		};
+
+		ocotp: nvmem@400a4000 {
+			compatible = "nxp,s32g2-ocotp";
+			reg = <0x400a4000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
 	};
 };
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 61ee08f0cfdc..8fe1fa35e9ac 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -765,6 +765,13 @@ gic: interrupt-controller@50800000 {
 			      <0x50420000 0x2000>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		ocotp: nvmem@400a4000 {
+			compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
+			reg = <0x400a4000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
 	};
 
 	timer {
-- 
2.47.2

Re: [PATCH V2 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver

[Frank Li]

On Tue, Aug 26, 2025 at 07:38:15PM +0300, Dan Carpenter wrote:
> Add the device tree information for the S32G On Chip One-Time
> Programmable Controller (OCOTP) chip.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
> v2: change "ocotp: ocotp@400a4000 {" to "ocotp: nvmem@400a4000 {"
>
>  arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++
>  arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++
>  2 files changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 6a7cc7b33754..e8cfddabfc24 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -701,5 +701,12 @@ gic: interrupt-controller@50800000 {
>  			interrupt-controller;
>  			#interrupt-cells = <3>;
>  		};
> +
> +		ocotp: nvmem@400a4000 {
> +			compatible = "nxp,s32g2-ocotp";
> +			reg = <0x400a4000 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +		};

Please keep order according to address,  0x400a4000 < 0x50800000

Frank Li

>  	};
>  };
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 61ee08f0cfdc..8fe1fa35e9ac 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -765,6 +765,13 @@ gic: interrupt-controller@50800000 {
>  			      <0x50420000 0x2000>;
>  			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>  		};
> +
> +		ocotp: nvmem@400a4000 {
> +			compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
> +			reg = <0x400a4000 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +		};
>  	};
>
>  	timer {
> --
> 2.47.2
>