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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?TOUb7a6kuUTzVn6YkR8f1Mh2asCRXXJMePiL3R5IpS1Xmckq2jxgLAw+5Mti?= =?us-ascii?Q?TlwlGq/tJqgQz57+yPDXhBkoBfkK2gCNpvMXU02Vv961QJizY7OIjG+KqvHp?= =?us-ascii?Q?idu3kborWyXScF/m2HGA6+nJjrbxfRYn4UVDKPE5Rnf4qzu+lk9JA7iVwaus?= =?us-ascii?Q?xSYXeapul7jLxYL+1ZNCU4UiHW7YIt/PwI43LNv2If6NWh8rHrDAVvWkczBA?= =?us-ascii?Q?OfYujV/LgOJeKOeEGlVv/b7MKwXS3p82Q0frzYPVhixKcrLdODTDmcW1UJGa?= =?us-ascii?Q?gCq1AR3skRyuOlsfU6jQdw1OgY8mt90laVs9BboREhrz2j49dqK1zodBDGZX?= =?us-ascii?Q?KLPS3kLcL6ZQZNcxfbtTQ1T/NEzt7OfaIK5V+rIHsNAO7J9rq5cP3bnKanr8?= =?us-ascii?Q?T69qinWsYvPEy76bRfL+buiwQasrqwDZcqOHtgwABR2WoSK+GCYShTUHU917?= =?us-ascii?Q?o95viTWwHNXS1tdv56d2bukRhOQtUA8JUiQ3MlwfsPWSQ3zew3KfHlehdb59?= =?us-ascii?Q?ku+CI+BuOh32IV6r1S1wJWHDNEEwefRkyz/sQZ8MOIc50olr8H9P7VONwsNb?= =?us-ascii?Q?qUQ5Iz3pRIdx5sU41slo9Y7lAIGKJJ6/8BXhgFPLz+voGp70WjfSrvgzWZ/u?= =?us-ascii?Q?JH6Uwy3K8oV0DtzVG/aP+3Sf85ri7Ic4dPfSioY05NkxQVVNcJoRMUg7vWxY?= =?us-ascii?Q?MOe/hu3EmCC52LVAsjsVX78YF0HrOPNfB/koZ6O+KOdmtqdW64WzUz+spTlU?= =?us-ascii?Q?UOgejHicTuh9ZLcr0Yt921vGtKOdAkf4LMD7BsjjrAqaEyJl4RISAQve58up?= =?us-ascii?Q?UUYEWU94q/DB1ruhoCWF4j/W8BaCJd2m/17JFeb1Q9GTWumJ9kh89TOHbVxb?= =?us-ascii?Q?LdM4jfO/d7pwd4pvHmlLYz0nOuVe8XWJANF9FtDoqffq9WJVX55+UI9N3b6h?= =?us-ascii?Q?aqeGXo+YPZ/r1gFCSbnIX2ixlGlCN0vXBfovatkrCErNSnGn1W+1e0dKZMZB?= =?us-ascii?Q?MKIkk6fQ24FS2Om38hQmxr4NI24ohI2Ic2sda2wUGqIxX9AC1zSUKnfC5Pq5?= =?us-ascii?Q?togQcY6ahIPoLuku7DOiU0qE2dnEmObZo0Q17pRiL3pRE4FQIldKwbzwrkd0?= =?us-ascii?Q?YU6QovjmhT9yENekE49OXplTvC2hrSNBPW5MYmffeWhyH4J8KANoBpm4uZcd?= =?us-ascii?Q?Dfut2ZTNUh1gG746Hvo/4YnFDiRcQzKYpQ8/OiFIG5xZWGRITUCNJlg6Cgwn?= =?us-ascii?Q?PfptVcnp8hXIvisXDBipe7W+vHOEFZoQI7xchyplIdANl/ZFd1eVoR8h2rrg?= =?us-ascii?Q?OpRA7GBK7EU9bhuWBkPLezy04uPuSvlS6ymyytA+FN+yapcs+1vgzFFutO0x?= =?us-ascii?Q?KzuRevpZ7iwqo1jzKX4IPskgk1+brD9YtZ3Cm5j0Z4F2ed2YCmjTaJQvBUtM?= =?us-ascii?Q?DFSKEubrXJ2kWTkh1anEwFXNjN8BUpXGcvqfkIVF+XyqIUx6xdhH7vnhZTMl?= =?us-ascii?Q?ItwSCPw1DTFp8Q8Y14+mh6YJGUbYxHfg9A4RxBGmTtqMUDSMAYbA7dYHxQML?= =?us-ascii?Q?ZiHdRMkbXe8ANlT+caXJQGU24RXbh2gX0eE6DXiR?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 046175a8-da0b-466e-f839-08de1706a543 X-MS-Exchange-CrossTenant-AuthSource: PAXSPRMB0053.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 16:17:24.4511 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: G4jw8dL56VAMUCPXwXwKcqAAnioUwOM6RSzecaYegS6XXKKgQzw5GixhuJe/ktnxe2A14gSTy7JoDnPZuhlueQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8124 On Wed, Oct 29, 2025 at 06:52:24AM -0700, Laurentiu Mihalcea wrote: > From: Laurentiu Mihalcea > > The i.MX8ULP System Integration Module (SIM) LPAV module is a block > control module found inside the LPAV subsystem, which offers some clock > gating options and reset line assertion/de-assertion capabilities. > > Therefore, the clock gate management is supported by registering the > module's driver as a clock provider, while the reset capabilities are > managed via the auxiliary device API to allow the DT node to act as a > reset and clock provider. > > Signed-off-by: Laurentiu Mihalcea > --- > drivers/clk/imx/Makefile | 1 + > drivers/clk/imx/clk-imx8ulp-sim-lpav.c | 160 +++++++++++++++++++++++++ > 2 files changed, 161 insertions(+) > create mode 100644 drivers/clk/imx/clk-imx8ulp-sim-lpav.c > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile > index 03f2b2a1ab63..208b46873a18 100644 > --- a/drivers/clk/imx/Makefile > +++ b/drivers/clk/imx/Makefile > @@ -41,6 +41,7 @@ clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o > clk-imx-acm-$(CONFIG_CLK_IMX8QXP) = clk-imx8-acm.o > > obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp.o > +obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp-sim-lpav.o > > obj-$(CONFIG_CLK_IMX1) += clk-imx1.o > obj-$(CONFIG_CLK_IMX25) += clk-imx25.o > diff --git a/drivers/clk/imx/clk-imx8ulp-sim-lpav.c b/drivers/clk/imx/clk-imx8ulp-sim-lpav.c > new file mode 100644 > index 000000000000..1614d9209734 > --- /dev/null > +++ b/drivers/clk/imx/clk-imx8ulp-sim-lpav.c > @@ -0,0 +1,160 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2025 NXP > + */ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define SYSCTRL0 0x8 > + > +#define IMX8ULP_HIFI_CLK_GATE(gname, cname, pname, bidx) \ > + { \ > + .name = gname "_cg", \ > + .id = IMX8ULP_CLK_SIM_LPAV_HIFI_##cname, \ > + .parent = { .fw_name = pname }, \ > + .bit = bidx, \ > + } > + > +struct clk_imx8ulp_sim_lpav_data { > + void __iomem *base; > + struct regmap *regmap; > + spinlock_t lock; /* shared by MUX, clock gate and reset */ > + unsigned long flags; /* for spinlock usage */ > + struct clk_hw_onecell_data clk_data; /* keep last */ > +}; > + > +struct clk_imx8ulp_sim_lpav_gate { > + const char *name; > + int id; > + const struct clk_parent_data parent; > + u8 bit; > +}; > + > +static struct clk_imx8ulp_sim_lpav_gate gates[] = { > + IMX8ULP_HIFI_CLK_GATE("hifi_core", CORE, "core", 17), > + IMX8ULP_HIFI_CLK_GATE("hifi_pbclk", PBCLK, "bus", 18), > + IMX8ULP_HIFI_CLK_GATE("hifi_plat", PLAT, "plat", 19) > +}; > + > +static void clk_imx8ulp_sim_lpav_lock(void *arg) __acquires(&data->lock) > +{ > + struct clk_imx8ulp_sim_lpav_data *data = dev_get_drvdata(arg); > + > + spin_lock_irqsave(&data->lock, data->flags); > +} > + > +static void clk_imx8ulp_sim_lpav_unlock(void *arg) __releases(&data->lock) > +{ > + struct clk_imx8ulp_sim_lpav_data *data = dev_get_drvdata(arg); > + > + spin_unlock_irqrestore(&data->lock, data->flags); > +} > + > +static const struct regmap_config clk_imx8ulp_sim_lpav_regmap_cfg = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > + .lock = clk_imx8ulp_sim_lpav_lock, > + .unlock = clk_imx8ulp_sim_lpav_unlock, > +}; > + > +static int clk_imx8ulp_sim_lpav_probe(struct platform_device *pdev) > +{ > + struct clk_imx8ulp_sim_lpav_data *data; > + struct regmap_config regmap_config; > + struct auxiliary_device *adev; > + struct clk_hw *hw; > + int i, ret; > + > + data = devm_kzalloc(&pdev->dev, > + struct_size(data, clk_data.hws, ARRAY_SIZE(gates)), > + GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + dev_set_drvdata(&pdev->dev, data); > + > + memcpy(®map_config, &clk_imx8ulp_sim_lpav_regmap_cfg, sizeof(regmap_config)); > + regmap_config.lock_arg = &pdev->dev; You copy clk_imx8ulp_sim_lpav_regmap_cfg to regmap_config and only once. look like not neccessary to use clk_imx8ulp_sim_lpav_regmap_cfg at all. struct regmap_config regmap_config = { .reg_bits = 32, .val_bits = 32, .reg_stride = 4, .lock = clk_imx8ulp_sim_lpav_lock, .unlock = clk_imx8ulp_sim_lpav_unlock, .lock_arg = &pdev->dev; }; it will be more straightforward. Frank > + > + /* > + * this lock is used directly by the clock gate and indirectly > + * by the reset and mux controller via the regmap API > + */ > + spin_lock_init(&data->lock); > + > + data->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(data->base)) > + return dev_err_probe(&pdev->dev, PTR_ERR(data->base), > + "failed to ioremap base\n"); > + /* > + * although the clock gate doesn't use the regmap API to modify the > + * registers, we still need the regmap because of the reset auxiliary > + * driver and the MUX drivers, which use the parent device's regmap > + */ > + data->regmap = devm_regmap_init_mmio(&pdev->dev, data->base, ®map_config); > + if (IS_ERR(data->regmap)) > + return dev_err_probe(&pdev->dev, PTR_ERR(data->regmap), > + "failed to initialize regmap\n"); > + > + data->clk_data.num = ARRAY_SIZE(gates); > + > + for (i = 0; i < ARRAY_SIZE(gates); i++) { > + hw = devm_clk_hw_register_gate_parent_data(&pdev->dev, > + gates[i].name, > + &gates[i].parent, > + CLK_SET_RATE_PARENT, > + data->base + SYSCTRL0, > + gates[i].bit, > + 0x0, &data->lock); > + if (IS_ERR(hw)) > + return dev_err_probe(&pdev->dev, PTR_ERR(hw), > + "failed to register %s gate\n", > + gates[i].name); > + > + data->clk_data.hws[i] = hw; > + } > + > + adev = devm_auxiliary_device_create(&pdev->dev, "reset", NULL); > + if (!adev) > + return dev_err_probe(&pdev->dev, -ENODEV, > + "failed to register aux reset\n"); > + > + ret = devm_of_clk_add_hw_provider(&pdev->dev, > + of_clk_hw_onecell_get, > + &data->clk_data); > + if (ret) > + return dev_err_probe(&pdev->dev, ret, > + "failed to register clk hw provider\n"); > + > + /* used to probe MUX child device */ > + return devm_of_platform_populate(&pdev->dev); > +} > + > +static const struct of_device_id clk_imx8ulp_sim_lpav_of_match[] = { > + { .compatible = "fsl,imx8ulp-sim-lpav" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, clk_imx8ulp_sim_lpav_of_match); > + > +static struct platform_driver clk_imx8ulp_sim_lpav_driver = { > + .probe = clk_imx8ulp_sim_lpav_probe, > + .driver = { > + .name = "clk-imx8ulp-sim-lpav", > + .of_match_table = clk_imx8ulp_sim_lpav_of_match, > + }, > +}; > +module_platform_driver(clk_imx8ulp_sim_lpav_driver); > + > +MODULE_LICENSE("GPL"); > +MODULE_DESCRIPTION("i.MX8ULP LPAV System Integration Module (SIM) clock driver"); > +MODULE_AUTHOR("Laurentiu Mihalcea "); > -- > 2.43.0 >