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Wed, 22 Apr 2026 09:25:08 -0700 (PDT) X-Received: by 2002:a0c:e007:0:b0:8ac:a893:8b5d with SMTP id 6a1803df08f44-8b027fd1849mr309815476d6.7.1776875107978; Wed, 22 Apr 2026 09:25:07 -0700 (PDT) Received: from rh-jkangas-kernel ([2601:1c2:4400:6bf0:7677:bcee:4ef0:e09d]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8b02ae7d79esm130910876d6.36.2026.04.22.09.25.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Apr 2026 09:25:07 -0700 (PDT) Date: Wed, 22 Apr 2026 09:25:03 -0700 From: Jared Kangas To: Dan Carpenter Cc: Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org, netdev@vger.kernel.org Subject: Re: [PATCH v6 3/3] dts: s32g: Add GPR syscon region Message-ID: References: <0e922537c02d1c47734142090f98eb78e921ed34.1769764941.git.dan.carpenter@linaro.org> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: scaueNGfbWQXSopqMOsgzeQuC7CWoSmZ4yrPYunoPLk_1776875108 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Apr 20, 2026 at 07:45:54PM +0300, Dan Carpenter wrote: > On Mon, Apr 20, 2026 at 09:04:00AM -0700, Jared Kangas wrote: > > Fixing Dan's address based on mailmap update, sorry for the noise. > > > > On Fri, Apr 17, 2026 at 02:36:25PM -0700, Jared Kangas wrote: > > > Hi Dan, > > > > > > [snip] > > > > > > I gave this a test on an S32G-VNP-RDB3 and didn't see any issues on the > > > dwmac-s32 side, but this appears to trigger a panic when reading the new > > > debugfs regmap/*/registers file for the syscon node: > > > > > > [snip] > > Oh, ugh... I didn't realize that this wasn't merged. I don't have a > way to test this any more. The simplest fix would be to do change the > 0x3000 to 0x100. The GPR63 register is at 0xFC. > > reg = <0x4007c000 0x100>; > > That's probably the best fix as well. The later register areas would > be their own syscons. Tried that out and it looks good to me. With the write routed through syscon: # xxd -g4 /proc/device-tree/soc@0/syscon@4007c000/reg 00000000: 4007c000 00000100 @....... # cat /sys/kernel/debug/regmap/dummy-syscon@0x000000004007c000/registers 00: 00000000 04: 00000002 08: 000000e7 0c: 00000001 10: ffffffff 14: 1fffffff 18: 00007fff 1c: 00000000 20: 00000000 ... f4: 00000000 f8: 00000000 fc: 00000000 No more crashes and 04's value lines up with the S32_PHY_INTF_SEL_RGMII (0x2) write, so if you're able to post a revision, feel free to add my T-b: Tested-by: Jared Kangas