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Mon, 31 Aug 2026 06:18:24 -0700 (PDT) Date: Mon, 31 Aug 2026 15:18:19 +0200 From: Stefano Radaelli To: sashiko-reviews@lists.linux.dev Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, imx@lists.linux.dev, Frank.Li@kernel.org Subject: Re: [PATCH v7 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support Message-ID: References: <20260831130506.94DB41F000E9@smtp.kernel.org> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260831130506.94DB41F000E9@smtp.kernel.org> On Mon, Aug 31, 2026 at 01:05:06PM +0000, sashiko-bot@kernel.org wrote: > > > diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi > > new file mode 100644 > > index 0000000000000..ab05de43cc53a > > --- /dev/null > > +++ b/arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi > > [ ... ] > > > +&i2c2 { > > + wm8731: audio-codec@1a { > > + compatible = "wlf,wm8731"; > > + reg = <0x1a>; > > + #sound-dai-cells = <0>; > > + AVDD-supply = <&vgen6_reg>; > > + DBVDD-supply = <&vgen6_reg>; > > + DCVDD-supply = <&vgen6_reg>; > > + HPVDD-supply = <&vgen6_reg>; > > + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; > > [Severity: High] > Does the codec driver incorrectly bind to IMX7D_AUDIO_MCLK_ROOT_DIV instead of > the physical SAI1 root clock driving the pin, causing the ASoC driver to read > an incorrect frequency? IMX7D_AUDIO_MCLK_ROOT_DIV is intentional here. The codec MCLK is provided by the dedicated audio MCLK root, while the SAI1 root clock is configured separately for the SAI interface. This configuration has also been validated on the hardware. > > > + clock-names = "mclk"; > > + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, > > + <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; > > + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; > > + assigned-clock-rates = <0>, <12288000>; > > + }; > > +}; > > + > > +&sai1 { > > + pinctrl-names = "default", "sleep"; > > + pinctrl-0 = <&pinctrl_sai1>, <&pinctrl_sai1_mclk>; > > + pinctrl-1 = <&pinctrl_sai1_sleep>, <&pinctrl_sai1_mclk_sleep>; > > + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, > > + <&clks IMX7D_SAI1_ROOT_CLK>; > > + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; > > + assigned-clock-rates = <0>, <36864000>; > > + status = "okay"; > > +}; > > [Severity: High] > Is the sai1 node missing the fsl,sai-mclk-direction-output property, leaving > the codec's MCLK pin undriven? > This is intentional. fsl,sai-mclk-direction-output is optional and is not required for this hardware configuration. The SAI1 MCLK pinmux and current clock setup have been validated on the board without this property. > > > +&i2c1 { > > + clock-frequency = <100000>; > > + pinctrl-names = "default", "gpio"; > > + pinctrl-0 = <&pinctrl_i2c1>; > > + pinctrl-1 = <&pinctrl_i2c1_gpio>; > > + scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > > + sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > > + status = "okay"; > > + > > + pfuze300: pmic@8 { > > + compatible = "fsl,pfuze3000"; > > + reg = <0x08>; > > + > > + regulators { > > + sw1a_reg: sw1a { > > + regulator-min-microvolt = <700000>; > > + regulator-max-microvolt = <3300000>; > > [Severity: High] > Is it safe to set regulator-max-microvolt to 3.3V for the VDD_ARM regulator? > Since this could allow the PMIC to supply up to 3.3V to the core, does this > exceed the i.MX7Dual hardware absolute maximum tolerances (around 1.3V)? This is intentional and matches the existing validated board configuration. The regulator constraints are not used to drive VDD_ARM to 3.3 V during normal operation.