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Wed, 14 Oct 2026 14:01:14 +0000 Date: Wed, 14 Oct 2026 09:01:04 -0500 From: Frank Li To: Alexander Stein Cc: Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dong Aisheng , Liu Ying , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com Subject: Re: [PATCH v2 3/5] arm64: dts: imx8qxp: Add MIPI-LVDS combo subsystems Message-ID: References: <20261014071657.118378-1-alexander.stein@ew.tq-group.com> <20261014071657.118378-4-alexander.stein@ew.tq-group.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261014071657.118378-4-alexander.stein@ew.tq-group.com> X-ClientProxiedBy: CYXPR03CA0022.namprd03.prod.outlook.com (2603:10b6:930:d0::20) To GV2PR04MB11799.eurprd04.prod.outlook.com (2603:10a6:150:2cf::9) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB11799:EE_|MIWPR04MB710340:EE_ X-MS-Office365-Filtering-Correlation-Id: dbb8dd8a-4ce2-4b1a-6a8d-08df29fb9c41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|19092799006|23010399003|366016|7416014|376014|1800799024|10067099003|18002099003|22082099003|3023799007|11063799006|261009223027099003|4143699003|56012099006; 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Add the MIPI-LVDS > combo subsystems. > > Signed-off-by: Liu Ying > Signed-off-by: Alexander Stein > --- > Changes in v2: > * None > > .../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 4 + > .../dts/freescale/imx8qxp-ss-mipi-lvds.dtsi | 443 ++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 3 + > 3 files changed, 450 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi > index 647ee3348f494..9916a06669c87 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi > @@ -156,10 +156,12 @@ port@1 { > > dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 { > reg = <0>; > + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>; > }; > > dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 { > reg = <1>; > + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>; > }; > }; > > @@ -211,10 +213,12 @@ port@1 { > > dc0_pixel_link1_mipi_lvds_1_pxl2dpi: endpoint@0 { > reg = <0>; > + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link1>; > }; > > dc0_pixel_link1_mipi_lvds_0_pxl2dpi: endpoint@1 { > reg = <1>; > + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link1>; > }; > }; > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi > new file mode 100644 > index 0000000000000..67f5392cfc803 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi > @@ -0,0 +1,443 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2024 NXP > + */ > + > +#include > +#include > + > +/ { > + mipi_lvds_0_ipg_clk: clock-mipi-lvds0-ipg { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <120000000>; > + clock-output-names = "mipi_lvds_0_ipg_clk"; > + }; > + > + mipi_lvds_1_ipg_clk: clock-mipi-lvds1-ipg { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <120000000>; > + clock-output-names = "mipi_lvds_1_ipg_clk"; > + }; > +}; > + > +&dc0_pl_msi_bus { > + mipi_lvds_0_irqsteer: interrupt-controller@56220000 { > + compatible = "fsl,imx-irqsteer"; > + reg = <0x56220000 0x1000>; > + interrupts = ; > + interrupt-controller; > + interrupt-parent = <&gic>; > + #interrupt-cells = <1>; > + clocks = <&mipi_lvds_0_lis_lpcg IMX_LPCG_CLK_4>; > + clock-names = "ipg"; > + fsl,channel = <0>; > + fsl,num-irqs = <32>; > + }; > + > + mipi_lvds_0_csr: bus@56221000 { > + compatible = "simple-pm-bus", "syscon"; > + reg = <0x56221000 0x1000>; > + clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; > + clock-names = "ipg"; > + #address-cells = <1>; > + #size-cells = <1>; Does any children nodes have address? > + ranges; > + > + mipi_lvds_0_pxl2dpi: pxl2dpi { > + compatible = "fsl,imx8qxp-pxl2dpi"; > + fsl,sc-resource = ; > + power-domains = <&pd IMX_SC_R_MIPI_0>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + > + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>; > + status = "disabled"; > + }; > + > + mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>; > + status = "disabled"; > + }; > + }; > + > + port@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + > + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; > + status = "disabled"; > + }; > + > + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; > + status = "disabled"; > + }; > + }; > + }; > + }; > + > + mipi_lvds_0_ldb: ldb { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx8qxp-ldb"; compatible should be first property, check others > + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, > + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; > + clock-names = "pixel", "bypass"; > + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>; > + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; > + power-domains = <&pd IMX_SC_R_LVDS_0>; > + status = "disabled"; > + > + channel@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; reg should be first one. Frank